Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

10.1. Features of the Hard Memory Controller

Table 31.  Hard Memory Controller Features
Feature Description
Protocol
  • LPDDR5—two dynamic frequency scaling (DFS) frequencies
  • DDR4 and DDR5—up to two chip selects and up to two 3D stacks
Interface
  • Fully pipelined command, read, and write data interfaces to the controller
  • Arm* AMBA* 4 AXI compliance including AXI ordering rules:
    • Four priority quality of service (QoS) levels
    • Programmable address mapping
    • Exclusive monitors
Scheduling
  • Software-configurable priority scheduling on individual SDRAM bursts
  • Advanced bank look-ahead features for high memory throughput
  • Configurable for one of these placement orders:
    • Out-of-order placement for writes
    • In-order placement for writes from the same port
    • In-order placement for writes from the same AXI master
  • Configurable for in-order scheduling for reads and writes
  • Support read or write grouping
Timing Fully programmable timing parameter support for all JEDEC* -specified timing parameters
Refresh
  • All bank refresh or per bank refresh (if supported by memory)
  • Refresh management for DDR5
ECC
  • Error correction code (ECC) support including calculation, error correction, write-back correction, and error counters
  • Hardened ECC support including configurations for various ECC types with programmable single-bit and double-bit error reporting and automatic correction:
    • In-line ECC, out-of-band ECC, link ECC, end-to-end (user) ECC, or no ECC
    • Supports standard single bit error correction and double bit error detection
    • Support for ECC passthrough for fabric ECC on a 8 bits of ECC per 64 bits of data
    • Supports scrubbing
Power states Low power DRAM states including active power down, precharge power down, and self-refresh power down states for DRAM:
  • Under register control; or
  • Based on idle times
Training Initial and periodic ZQ calibration (LPDDR4, LPDDR5, DDR5)
Verification
  • Performance monitoring statistics
  • Memory test for DDR memories through register control

Did you find the information on this page useful?

Characters remaining:

Feedback Message