Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/31/2023
Public
Document Table of Contents

6. Variable-Precision DSP in Intel Agilex® 7 FPGAs and SoCs

The Intel Agilex® 7 FPGAs and SoCs carry over the variable-precision DSP architecture from previous Intel® FPGAs with hard fixed point and IEEE 754-compliant floating point capabilities.

In fixed point mode, you can configure the DSP blocks to support signal processing with precisions from 9×9 up to 54×54:

  • Increased 9×9 multipliers count, with three 9×9 multipliers for every 18×19 multiplier
  • A pipeline register increases the maximum DSP block operating frequency and reduces the power consumption
  • Dynamically switch multiplier inputs through scanin and chainout signals
  • Compile each DSP block independently as four 9×9, two 18×19, or one 27×27 multiply-accumulate

The variable-precision DSP supports floating point addition, multiplication, multiply-add, and multiply-accumulate:

  • Single-precision 32-bit arithmetic FP32 floating point mode
  • Half-precision 16-bit arithmetic FP16 and FP19 floating point modes, and BFLOAT16 floating point format

With a dedicated 64-bit cascade bus, you can cascade multiple variable-precision DSP blocks to efficiently implement even higher-precision DSP functions.

Figure 7. Low Precision Fixed Point Mode
Figure 8. Standard Precision Fixed Point Mode
Figure 9. High Precision Fixed Point Mode
Figure 10. Half Precision 16-bit Arithmetic Floating PointThis block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Figure 11. Single Precision 32-bit Arithmetic Floating PointThis block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Table 22.  Variable-Precision DSP Block Configurations in Intel Agilex® 7 FPGAs and SoCs This table lists the way Intel Agilex® 7 FPGAs and SoCs accommodate the different precisions within a DSP block or by utilizing multiple DSP blocks.
Multiplier DSP Block Resource Usage Expected Application
9×9 bits

One-fourth of a variable-precision DSP block

(One DSP block can support four 9×9)

Low-precision fixed point
18×19 bits Half of a variable-precision DSP block Medium-precision fixed point
27×27 bits One variable-precision DSP block High-precision fixed point
19×36 bits One variable-precision DSP block with external adder Fixed point fast Fourier transform (FFT)
36×36 bits Two variable-precision DSP blocks with external adder Very high-precision fixed point
54×54 bits Four variable-precision DSP blocks with external adder Double-precision fixed point
Half-precision floating point

One variable-precision DSP block

(Contains adder for two FP16 multipliers with one accumulator)

Half-precision floating point
Single-precision floating point

One variable-precision DSP block

(Contains one FP32 multipliers with one accumulator)

Single-precision floating point