Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs

The Intel® Agilex™ FPGAs and SoCs also carry over the variable-precision DSP architecture from previous Intel® FPGAs with hard fixed point and IEEE 754-compliant floating point capabilities.

In fixed point mode, you can configure the DSP blocks to support signal processing with precisions from 9×9 up to 54×54:

  • Increased 9×9 multipliers count, with three 9×9 multipliers for every 18×19 multiplier
  • A pipeline register increases the maximum DSP block operating frequency and reduces the power consumption
  • Dynamically switch multiplier inputs through scanin and chainout signals
  • Compile each DSP block independently as six40 or four41 9×9, two 18×19, or one 27×27 multiply-accumulate.

The variable-precision DSP supports floating point addition, multiplication, multiply-add, and multiply-accumulate:

  • Single-precision 32-bit arithmetic FP32 floating point mode
  • Half-precision 16-bit arithmetic FP16 and FP19 floating point modes, and BFLOAT16 floating point format

With a dedicated 64-bit cascade bus, you can cascade multiple variable-precision DSP blocks to efficiently implement even higher-precision DSP functions.

Figure 8. Low Precision Fixed Point Mode
Figure 9. Standard Precision Fixed Point Mode
Figure 10. High Precision Fixed Point Mode
Figure 11. Half Precision 16-bit Arithmetic Floating PointThis block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Figure 12. Single Precision 32-bit Arithmetic Floating PointThis block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.

Additionally, Intel® Agilex™ D-Series devices are the first midrange FPGAs with an AI tensor block, making it the ideal choice for edge AI applications. For INT8 operations in a single DSP block, Intel® Agilex™ D-Series devices improve peak theoretical TOPS up to two times than Intel® Stratix® 10 FPGAs. Through a large increase in arithmetic density42 , the Intel® Agilex™ D-Series FPGAs and SoCs fit more multipliers and accumulators in the same footprint of a standard DSP block.

Table 25.  Variable-Precision DSP Block Configurations in Intel® Agilex™ FPGAs and SoCsThis table lists the way Intel® Agilex™ devices accommodate the different precisions within a DSP block or by utilizing multiple DSP blocks.
Multiplier DSP Block Resource Usage Expected Application

F-Series, I-Series, and M-Series

D-Series
9×9 bits

One-fourth of Variable Precision DSP Block

(One DSP block can support four 9×9)

One-sixth of of a variable-precision DSP block

(One DSP block can support six 9×9)

Low-precision fixed point
18×19 bits Half of a variable-precision DSP block Medium-precision fixed point
27×27 bits One variable-precision DSP block High-precision fixed point
19×36 bits One variable-precision DSP block with external adder Fixed point fast Fourier transform (FFT)
36×36 bits Two variable-precision DSP blocks with external adder Very high-precision fixed point
54×54 bits Four variable-precision DSP blocks with external adder Double-precision fixed point
Half-precision floating point

One variable-precision DSP block

(Contains adder for two FP16 multipliers with one accumulator)

One variable-precision DSP block

(Contains adder for two FP16, FP19, or BFLOAT16 multipliers with one accumulator)

Half-precision floating point
Single-precision floating point

One variable-precision DSP block

(Contains one FP32 multipliers with one accumulator)

Single-precision floating point
AI tensor block Two sums of ten INT8×INT8 multipliers tensor fixed- and floating-point computation Tensor dot products of 10-element vectors computation
Complex multiplication mode

One variable-precision DSP block

(16×16 ± 16×16)

INT16 complex multiplication
40 Applicable to Intel® Agilex™ D-Series devices.
41 Applicable to Intel® Agilex™ F-Series, I-Series, and M-Series devices.
42 Arithmetic density is a measure of how many dot products can fit into a 1 mm2 of silicon on any given process node.

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