Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

22. Power Management for Intel® Agilex™ FPGAs and SoCs

The Intel® Agilex™ FPGAs and SoCs device family offers standard power devices that support SmartVID and fixed core voltage devices with limited core speed options.

The Intel® Agilex™ FPGAs and SoCs achieve up to 42% total power reduction compared to the previous generation Intel® Stratix® 10 FPGAs by capitalizing on:

  • Advanced Intel® 10-nm SuperFin and Intel® 7 technologies
  • Second generation Intel® Hyperflex™ core architecture
  • SmartVID or fixed core voltage
  • Other power reduction techniques such as power island and power gating
Table 43.   Intel® Agilex™ F-Series, I-Series, and M-Series FPGAs and SoCs Power Options
Device Type Series Designation Description
SmartVID

F-Series

I-Series

M-Series

-V
  • The devices operate at the optimum core voltage that meets the VID power limit and required device performance for various FPGA applications.
  • A factory-programmed code allows a PMBus voltage regulator to operate at the optimum core voltage to meet the device VID power limit and performance specifications. Therefore, you must mandatorily drive the VCC and VCCP core voltage supplies of the Intel® Agilex™ SmartVID device with a dedicated PMBus voltage regulator.
Fixed voltage F-Series -F
  • The devices support 0.8 V. Using a fixed 0.8 V core voltage,the devices further reduce the total power consumption.
  • These fixed voltage devices have lower static power than the SmartVID standard power devices while maintaining device performance.

The power island and power gating feature powers down unused resources in Intel® Agilex™ devices to reduce static power consumption. During configuration, the Intel® Quartus® Prime software automatically powers down specific unused resources such as the DSP or M20K blocks.

Furthermore, Intel® Agilex™ devices feature industry-leading low power transceivers and include a number of hard IP blocks. The hard IP blocks not only reduce logic resources utilization but also deliver substantial power savings compared to soft implementations. The hard IP blocks generally consume up to 50% less power than equivalent soft logic implementations.

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