Intel Agilex® 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/31/2023
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20. Power Management for Intel Agilex® 7 FPGAs and SoCs

The Intel Agilex® 7 FPGA product family offers standard power devices that support SmartVID and fixed core voltage devices with limited core speed options.

The Intel Agilex® 7 FPGAs and SoCs achieve up to 40% total power reduction compared to the previous generation Intel® Stratix® 10 FPGAs.

To achieve the total power reduction, the Intel Agilex® 7 FPGAs and SoCs capitalizes on:

  • Advanced Intel® 10-nm SuperFin or Intel® 7 technology
  • Second generation Intel® Hyperflex™ core architecture
  • SmartVID or fixed core voltage
  • Other power reduction techniques such as power island and power gating
Table 35.   Intel Agilex® 7 FPGAs and SoCs Power Options
Device Type Series Designation Description
SmartVID

F-Series

I-Series

M-Series

-V
  • The devices operate at the optimum core voltage that meets the VID power limit and required device performance for various FPGA applications.
  • A factory-programmed code allows a PMBus voltage regulator to operate at the optimum core voltage to meet the device VID power limit and performance specifications. Therefore, you must mandatorily drive the VCC and VCCP core voltage supplies of the SmartVID device with a dedicated PMBus voltage regulator.
Fixed voltage F-Series -F
  • The devices support 0.8 V.
  • Using a fixed low core voltage,the devices further reduce the total power consumption.
  • These fixed voltage devices have lower static power than the SmartVID standard power devices while maintaining device performance.

The power island and power gating feature powers down unused resources in Intel Agilex® 7 devices to reduce static power consumption. During configuration, the Intel® Quartus® Prime software automatically powers down specific unused resources such as the DSP or M20K blocks.

Furthermore, Intel Agilex® 7 devices feature industry-leading low power transceivers and include a number of hard IP blocks. The hard IP blocks not only reduce logic resources utilization but also deliver substantial power savings compared to soft implementations. The hard IP blocks generally consume up to 50% less power than equivalent soft logic implementations.