Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

12.1. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ F-Series, I-Series, and M-Series FPGAs and SoCs

The transceivers in the Intel® Agilex™ F-Series, I-Series, and M-Series FPGAs and SoCs are low-latency power efficient transceivers with a high bandwidth capacity.

Intel implements the Intel® Agilex™ F-Series, I-Series, and M-Series transceivers on heterogeneous 3D system-in-package (SiP) transceiver tiles. This high-performance transceiver solution provides flexibility and scalability for current and future data rates, modulation schemes, and protocol IPs.

Figure 16. Core Fabric and Heterogeneous 3D SiP Transceiver Tiles


Table 34.  Types and Capabilities of Intel® Agilex™ F-Series, I-Series, and M-Series Transceivers
Tile Type General Description Maximum Data Rate and Channel Count Hardened IP Applications
E-Tile General purpose transceiver 12×58 Gbps PAM4 or 24×28.9 Gbps NRZ
  • 10/25/100 GbE MAC, PCS and RS-FEC (528,514)
  • RS-FEC (544,514)
  • General purpose transceivers
  • Multi-protocol support for CEI, Ethernet, CPRI, FlexE, Interlaken, Fibre Channel, SRIO, Serial Lite, OTN, JESD204B/C, FlexO, IEEE1588
P-Tile PCIe* 4.0 transceiver 16×16 Gbps NRZ 16× PCIe* 4.0 with 8 PF/2K VF SR-IOV EP/RP

PCIe Gen4 x16 including port bifurcation support for 2x8 EP or 4x4 RP, CvP , Autonomous HIP, SR-IOV 8PF / 2kVF, VirtIO, Scalable IOV and Shared Virtual Memory

F-Tile General purpose and PCIe* 4.0 transceiver 116 Gbps PAM4, 12×58 Gbps PAM4, or 16×32 Gbps NRZ
  • 10/25/40/50/100/200/400 GbE MAC, PCS, and KR/KP RS-FEC
  • 16× PCIe* 4.0 with 8 PF/2K VF SR-IOV EP/RP

General Purpose Transceiver with multi-protocol support for CEI, Ethernet, CPRI, FlexE, 300G Interlaken, Fibre Channel, SRIO, Serial Lite, OTN, JESD204B/C, IEEE1588, FlexO, GPON, SDI, Vby1, HDMI, CvP, Display Port, P-Tile PCIe features plus Precise Time Management and PMA direct mode

R-Tile PCIe* 5.0 and CXL* transceiver 16×32 Gbps NRZ
  • 16× PCIe* 5.0 with 8 PF/2K VF SR-IOV EP/RP
  • 16× CXL*

PCIe Gen5 x16 including port bifurcation support for 2x8 EP or 4x4 RP, CvP, Autonomous HIP, SR-IOV 8PF / 2kVF, VirtIO, Scalable IOV, and Shared Virtual Memory, separate header and payload interfaces on user interface, Precise Time Management, PIPE Direct

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