12.1. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ F-Series, I-Series, and M-Series FPGAs and SoCs
Intel implements the Intel® Agilex™ F-Series, I-Series, and M-Series transceivers on heterogeneous 3D system-in-package (SiP) transceiver tiles. This high-performance transceiver solution provides flexibility and scalability for current and future data rates, modulation schemes, and protocol IPs.
|Tile Type||General Description||Maximum Data Rate and Channel Count||Hardened IP||Applications|
|E-Tile||General purpose transceiver||12×58 Gbps PAM4 or 24×28.9 Gbps NRZ||
|P-Tile||PCIe* 4.0 transceiver||16×16 Gbps NRZ||16× PCIe* 4.0 with 8 PF/2K VF SR-IOV EP/RP||
PCIe Gen4 x16 including port bifurcation support for 2x8 EP or 4x4 RP, CvP , Autonomous HIP, SR-IOV 8PF / 2kVF, VirtIO, Scalable IOV and Shared Virtual Memory
|F-Tile||General purpose and PCIe* 4.0 transceiver||4×116 Gbps PAM4, 12×58 Gbps PAM4, or 16×32 Gbps NRZ||
General Purpose Transceiver with multi-protocol support for CEI, Ethernet, CPRI, FlexE, 300G Interlaken, Fibre Channel, SRIO, Serial Lite, OTN, JESD204B/C, IEEE1588, FlexO, GPON, SDI, Vby1, HDMI, CvP, Display Port, P-Tile PCIe features plus Precise Time Management and PMA direct mode
|R-Tile||PCIe* 5.0 and CXL* transceiver||16×32 Gbps NRZ||
PCIe Gen5 x16 including port bifurcation support for 2x8 EP or 4x4 RP, CvP, Autonomous HIP, SR-IOV 8PF / 2kVF, VirtIO, Scalable IOV, and Shared Virtual Memory, separate header and payload interfaces on user interface, Precise Time Management, PIPE Direct
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