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1. Overview of the Intel Agilex® 7 FPGAs and SoCs
2. Intel Agilex® 7 FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex™ Core Architecture
4. Adaptive Logic Module in Intel Agilex® 7 FPGAs and SoCs
5. Internal Embedded Memory in Intel Agilex® 7 FPGAs and SoCs
6. Variable-Precision DSP in Intel Agilex® 7 FPGAs and SoCs
7. Core Clock Network in Intel Agilex® 7 FPGAs and SoCs
8. General Purpose I/Os in Intel Agilex® 7 FPGAs and SoCs
9. I/O PLLs in Intel Agilex® 7 FPGAs and SoCs
10. External Memory Interface in Intel Agilex® 7 FPGAs and SoCs
11. Hard Processor System in Intel Agilex® 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Intel Agilex® 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel Agilex® 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Intel Agilex® 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Intel Agilex® 7 FPGAs and SoCs
16. Device Configuration and the SDM in Intel Agilex® 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Intel Agilex® 7 FPGAs and SoCs
18. Device Security for Intel Agilex® 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Intel Agilex® 7 FPGAs and SoCs
20. Power Management for Intel Agilex® 7 FPGAs and SoCs
21. Intel® Software and Tools for Intel Agilex® 7 FPGAs and SoCs
22. Revision History for the Intel Agilex® 7 FPGAs and SoCs Device Overview
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8. General Purpose I/Os in Intel Agilex® 7 FPGAs and SoCs
The Intel Agilex® 7 FPGAs and SoCs are equipped with general purpose I/Os (GPIO) that support various I/O standards from 1.05 V to 1.5 V.
In each GPIO bank, there are two 48-pin sub-banks, providing a total of 96 pins per bank. In the M-Series FPGAs, each sub-bank has its own VCCIO.
I/O Standard | Series | Specification | Notes |
---|---|---|---|
LVCMOS/LVTTL | F-Series I-Series |
1.2 V single-ended | — |
M-Series |
1.05 V, 1.1 V, and 1.2 V single-ended | ||
TDS | F-Series I-Series |
|
Works with the LVDS SERDES Intel® FPGA IP |
M-Series |
|