Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 4/01/2024
Document Table of Contents

19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs

Agilex™ 7 devices feature a robust SEU error detection and correction circuitry that protects the configuration RAM (CRAM) programming bits and M20K user memories.

To protect the CRAM, a parity checker circuit with integrated ECC runs continuously to automatically correct single-bit or double-bit errors and detect higher order multi-bit errors. The optimized physical layout of the CRAM array makes most multi-bit upsets appear as independent single-bit or double-bit errors. Therefore, the CRAM ECC circuitry can automatically correct these errors.

The user memories also has integrated ECC circuitry and are also layout-optimized for error detection and correction.

To provide a complete SEU mitigation solution, a soft IP and the Quartus® Prime software support the SEU error detection and correction hardware. The following components make up the complete solution:

  • Hard error detection and correction for CRAM and M20K user memory blocks
  • Optimized memory cells physical layout to minimize the probability of an SEU
  • Sensitivity processing soft IP that reports if a CRAM upset affects a used or unused bit
  • Fault injection soft IP with Quartus® Prime software support to change CRAM bits state for testing
  • Hierarchy tagging feature in the Quartus® Prime software
  • Triple modular redundancy (TMR) for the SDM and critical on-chip state machines

Furthermore, Agilex™ 7 FPGAs and SoCs are built on the FinFET-based Intel® 10-nm SuperFin or Intel® 7 technology. FinFET transistors are less susceptible to SEUs compared to conventional planar transistors.