Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs

Intel® Agilex™ devices feature a robust SEU error detection and correction circuitry that protects the configuration RAM (CRAM) programming bits and M20K user memories.

To protect the CRAM, a parity checker circuit with integrated ECC runs continuously to automatically correct single-bit or double-bit errors and detect higher order multi-bit errors. The optimized physical layout of the CRAM array makes most multi-bit upsets appear as independent single-bit or double-bit errors. Therefore, the CRAM ECC circuitry can automatically correct these errors.

The user memories also has integrated ECC circuitry and are also layout-optimized for error detection and correction.

To provide a complete SEU mitigation solution, a soft IP and the Intel® Quartus® Prime software support the SEU error detection and correction hardware. The following components make up the complete solution:

  • Hard error detection and correction for CRAM and M20K user memory blocks
  • Optimized memory cells physical layout to minimize the probability of an SEU
  • Sensitivity processing soft IP that reports if a CRAM upset affects a used or unused bit
  • Fault injection soft IP with Intel® Quartus® Prime software support to change CRAM bits state for testing
  • Hierarchy tagging feature in the Intel® Quartus® Prime software
  • Triple modular redundancy (TMR) for the SDM and critical on-chip state machines

Furthermore, Intel® Agilex™ FPGAs and SoCs are built on the FinFET-based Intel® 10-nm SuperFin or Intel® 7 technology. FinFET transistors are less susceptible to SEUs compared to conventional planar transistors.

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