10. External Memory Interface in Intel Agilex® 7 FPGAs and SoCs
Each I/O bank contains 96 general purpose I/Os and two high-efficiency hard memory controllers. The hard memory controllers support various memory types, each with different performance capabilities. You can bypass the hard memory controller and implement a soft memory controller in user logic.
Each I/O contains a hard DDR read and write path (PHY) capable of performing key memory interface functions such as:
- Read and write leveling
- FIFO buffering to lower latency and improve margin
- Timing calibration
- On-chip termination
Hard microcontrollers aid the timing calibration. Intel customized these hard microcontrollers to control the calibration of multiple memory interfaces. The calibration enables the Intel Agilex® 7 device to compensate for process, voltage, and temperature (PVT) variance within the Intel Agilex® 7 device or the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.