Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 4/01/2024
Document Table of Contents

10. External Memory Interface in Agilex™ 7 FPGAs and SoCs

The Agilex™ 7 FPGAs and SoCs feature a substantial external memory bandwidth. This bandwidth is accompanied by the ease-of-design, lower power, and resource efficiencies of high-performance hard memory controllers. Using the hard or soft memory controller, you can configure external memory interfaces width up to a maximum of 72 bits.
Figure 12. Hard Memory Controller

Each I/O bank contains 96 general purpose I/Os and two high-efficiency hard memory controllers. The hard memory controllers support various memory types, each with different performance capabilities. You can bypass the hard memory controller and implement a soft memory controller in user logic.

Each I/O contains a hard DDR read and write path (PHY) capable of performing key memory interface functions such as:

  • Read and write leveling
  • FIFO buffering to lower latency and improve margin
  • Timing calibration
  • On-chip termination

Hard microcontrollers aid the timing calibration. Intel customized these hard microcontrollers to control the calibration of multiple memory interfaces. The calibration enables the Agilex™ 7 device to compensate for process, voltage, and temperature (PVT) variance within the Agilex™ 7 device or the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.