Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs

The Intel® Agilex™ FPGAs and SoCs feature a substantial external memory bandwidth. This bandwidth is accompanied by the ease-of-design, lower power, and resource efficiencies of high-performance hard memory controllers. Using the hard or soft memory controller, you can configure external memory interfaces width up to a maximum of 72 bits.
Figure 13. Hard Memory Controller

Each I/O bank contains 96 general purpose I/Os and two high-efficiency hard memory controllers. The hard memory controllers support various memory types, each with different performance capabilities. You can bypass the hard memory controller and implement a soft memory controller in user logic.

Each I/O contains a hard DDR read and write path (PHY) capable of performing key memory interface functions such as:

  • Read and write leveling
  • FIFO buffering to lower latency and improve margin
  • Timing calibration
  • On-chip termination
Table 28.  External Memory Interface Performance— Intel® Agilex™ F-Series and I-Series FPGAs
Interface Protocol Memory Controller Interface Performance (Mbps) Maximum Width (Bits)
DDR4 Hard 3,200 64 / 72
QDRIV Soft 2,133 36
Table 29.  External Memory Interface Performance— Intel® Agilex™ M-Series FPGAs
Interface Protocol Memory Controller Interface Performance (Mbps) Maximum Width (Bits)
DDR4 Hard 3,200 Component 40
DIMM 72
DDR5 Hard 5,600 Component 40
DIMM 2×40
LPDDR5 Hard 5,500 4×16
QDRIV Soft 2,133 36
Table 30.  External Memory Interface Performance in Intel® Agilex™ D-Series FPGAs and SOCs
Interface Protocol Memory Controller Interface Performance (Mbps) Maximum Width (Bits)
DDR4 Hard 3,200 64 / 72
DDR5 Hard 4,000 32 / 40
LPDDR4/4X Hard 4,267 32 / 40
LPDDR5 Hard 4,267 32 / 40

Hard microcontrollers aid the timing calibration. Intel customized these hard microcontrollers to control the calibration of multiple memory interfaces. The calibration enables the Intel® Agilex™ device to compensate for process, voltage, and temperature (PVT) variance within the Intel® Agilex™ device or the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.

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