Intel® Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458
Date 1/10/2023
Public
Document Table of Contents
Document Table of Contents
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs 2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Intel® Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Intel® Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Intel® Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Intel® Agilex™ 7 FPGAs and SoCs 18. Device Security for Intel® Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Intel® Agilex™ 7 FPGAs and SoCs 20. Power Management for Intel® Agilex™ 7 FPGAs and SoCs 21. Intel® Software and Tools for Intel® Agilex™ 7 FPGAs and SoCs 22. Revision History for the Intel® Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs
1.1. Key Features and Innovations in Intel® Agilex™ 7 FPGAs and SoCs 1.2. Intel® Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Intel® Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Intel® Agilex™ 7 SoCs
2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan
2.1. Intel® Agilex™ 7 FPGAs and SoCs F-Series 2.2. Intel® Agilex™ 7 FPGAs and SoCs I-Series 2.3. Intel® Agilex™ 7 FPGAs and SoCs M-Series 2.4. Available Options
10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs
2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex™ Core Architecture
4. Adaptive Logic Module in Intel® Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Intel® Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Intel® Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Intel® Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Intel® Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Intel® Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Intel® Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Intel® Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Intel® Agilex™ 7 FPGAs and SoCs
18. Device Security for Intel® Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Intel® Agilex™ 7 FPGAs and SoCs
20. Power Management for Intel® Agilex™ 7 FPGAs and SoCs
21. Intel® Software and Tools for Intel® Agilex™ 7 FPGAs and SoCs
22. Revision History for the Intel® Agilex™ 7 FPGAs and SoCs Device Overview

9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs

The I/O banks of the Intel® Agilex™ 7 FPGAs and SoCs contain I/O PLLs for use in I/O interfacing or fabric clocking.
Table 24.  I/O PLLs in I/O Banks
Series Bank I/O PLL Fabric-Feeding I/O PLL
F-Series 2 1
I-Series 2 1
M-Series 2 1

You can use the I/O PLLs for general purpose applications in the core fabric, such as clock network delay compensation and zero-delay clock buffering.

The I/O PLLs are situated adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O bank. This placement creates a tight coupling of the PLLs with the I/Os that need them. The architecture simplifies designing external memory and high-speed LVDS interfaces, and eases timing closure.

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