Intel® Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 1/10/2023
Public
Document Table of Contents

9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs

The I/O banks of the Intel® Agilex™ 7 FPGAs and SoCs contain I/O PLLs for use in I/O interfacing or fabric clocking.
Table 24.  I/O PLLs in I/O Banks
Series Bank I/O PLL Fabric-Feeding I/O PLL
F-Series 2 1
I-Series 2 1
M-Series 2 1

You can use the I/O PLLs for general purpose applications in the core fabric, such as clock network delay compensation and zero-delay clock buffering.

The I/O PLLs are situated adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O bank. This placement creates a tight coupling of the PLLs with the I/Os that need them. The architecture simplifies designing external memory and high-speed LVDS interfaces, and eases timing closure.

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