Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs

Intel built the partial reconfiguration process on top of the proven incremental compile design flow in the Intel® Quartus® Prime design software. With partial reconfiguration, you can reconfigure parts of the FPGA while other sections continue to run. In systems with critical uptime requirement, you can update or adjust functions without disrupting service provision.

Apart from lowering power usage and cost, partial configuration effectively increases the logic density. Instead of placing all functions in the FPGA from the start, you can store functions that do not have to operate simultaneously in external memory. You can load these function into the FPGA when needed. Using this technique, you can run multiple applications on a single FPGA and reduce the requirements for FPGA size, board space, and power.

With dynamic reconfiguration, Intel® Agilex™ devices can dynamically change data rates, protocols, and analog settings of a transceiver channel without affecting data transfer on adjacent transceiver channels. This capability is ideal for applications that require on-the-fly multi-protocol or multi-rate support.

You can dynamically reconfigure both the PMA and PCS blocks within the transceiver. You can also use dynamic reconfiguration together with partial reconfiguration to partially reconfigure the FPGA core and transceivers simultaneously.

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