Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 4/01/2024
Document Table of Contents

12.1.2. PCS Features in E-Tile Transceivers

The PMA channels in the E-Tile transceivers interface with the core logic through the configurable and bypassable PCS interface layers.

The PCS contains multiple gearbox implementations to decouple the PMA and PCS interface widths. The gearbox implementations provide the flexibility to implement a wide range of applications with 8, 10, 16, 20, 32, 40, or 64 bits interface width between each transceiver and the core logic.

The PCS hard IP supports various standard and proprietary protocols across a wide range of data rates and encoding schemes.

Table 31.  E-Tile PCS Modes
Mode Description
Standard PCS Provides support for 8B/10B encoded applications up to 12.5 Gbps
Enhanced PCS
  • Supports 64B/66B and 64B/67B encoded applications up to 58 Gbps
  • Includes an integrated KP and KR forward error correction (FEC) circuit
PCS Direct
  • For highly customized implementations
  • Provides an interface up to 64 bits wide to allow custom encoding and support for data rates up to 28.9 Gbps