Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

3. Second Generation Intel® Hyperflex™ Core Architecture

The Intel® Agilex™ FPGAs and SoCs are based on a core fabric featuring the second generation Intel® Hyperflex™ core architecture.
Table 22.  Advantages of the Intel® Hyperflex™ Core ArchitectureThis table lists some of the advantages of the Intel® Hyperflex™ core architecture.
Advantage Description
Higher throughput

Delivers, on average, 50% higher core clock frequency performance in designs from previous generation high-end FPGAs to obtain throughput breakthroughs.

Improved power efficiency Uses reduced IP size to consolidate designs that previously spanned multiple devices into a single device. This consolidation reduces power requirement by up to 42% compared to previous generation devices.
Greater design functionality Uses faster clock frequency to reduce bus widths and reduce IP size. The reduced bus widths and IP size free up additional FPGA resources to add greater functionality.
Increased designer productivity Boosts performance with less routing congestion and fewer design iterations using the Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure.

Additional to traditional ALM user registers, the Intel® Hyperflex™ core architecture adds bypassable registers called Hyper-Registers:

  • Distributed throughout the FPGA fabric.
  • Available on every interconnect routing segment and at the inputs of all functional blocks.
Figure 5. Bypassable Hyper Register

In the second generation Intel® Hyperflex™ core architecture, Intel optimized the number of registers to improve timing closure time and fabric area utilization.

Figure 6.  Intel® Hyperflex™ Core Architecture

The Hyper-Registers enable you to achieve core performance increases using key design techniques. If you implement these design techniques, the Hyper-Aware design tools automatically utilizes the Hyper-Registers to achieve maximum core clock frequency:

  • Fine grain Hyper-Retiming to eliminate critical paths
  • Zero-latency Hyper-Pipelining to eliminate routing delays
  • Flexible Hyper-Optimization for best-in-class performance

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