3. Second Generation Intel® Hyperflex™ Core Architecture
Delivers, on average, 50% higher core clock frequency performance in designs from previous generation high-end FPGAs to obtain throughput breakthroughs.
|Improved power efficiency||Uses reduced IP size to consolidate designs that previously spanned multiple devices into a single device. This consolidation reduces power requirement by up to 42% compared to previous generation devices.|
|Greater design functionality||Uses faster clock frequency to reduce bus widths and reduce IP size. The reduced bus widths and IP size free up additional FPGA resources to add greater functionality.|
|Increased designer productivity||Boosts performance with less routing congestion and fewer design iterations using the Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure.|
Additional to traditional ALM user registers, the Intel® Hyperflex™ core architecture adds bypassable registers called Hyper-Registers:
- Distributed throughout the FPGA fabric.
- Available on every interconnect routing segment and at the inputs of all functional blocks.
In the second generation Intel® Hyperflex™ core architecture, Intel optimized the number of registers to improve timing closure time and fabric area utilization.
The Hyper-Registers enable you to achieve core performance increases using key design techniques. If you implement these design techniques, the Hyper-Aware design tools automatically utilizes the Hyper-Registers to achieve maximum core clock frequency:
- Fine grain Hyper-Retiming to eliminate critical paths
- Zero-latency Hyper-Pipelining to eliminate routing delays
- Flexible Hyper-Optimization for best-in-class performance
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