Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458
Date 3/18/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 7 FPGAs and SoCs 2. Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs 18. Device Security for Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs 20. Power Management for Agilex™ 7 FPGAs and SoCs 21. Software and Tools for Agilex™ 7 FPGAs and SoCs 22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 7 FPGAs and SoCs 1.2. Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 7 SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Agilex™ 7 FPGAs and SoCs F-Series 2.2. Agilex™ 7 FPGAs and SoCs I-Series 2.3. Agilex™ 7 FPGAs and SoCs M-Series 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview

1.1. Key Features and Innovations in Agilex™ 7 FPGAs and SoCs

With the power and performance efficiency of industry-leading Intel® 10-nm SuperFin and Intel® 7 technologies, the Agilex™ 7 FPGAs and SoCs are available in several series.
Table 1.   Agilex™ 7 FPGAs and SoCs Series
Feature and Innovation F-Series FPGA I-Series FPGA M-Series FPGA
Application optimization For a wide range of applications that require optimal balance of power and performance For high performance processor interface and bandwidth-intensive applications For compute-intensive, high-memory bandwidth applications
Process technology Intel® 10-nm SuperFin Intel® 10-nm SuperFin Intel® 7
Architecture Chiplet architecture
Packaging Rectangular package and hex pattern ball array for more functionality per area
Core fabric Second generation Hyperflex® core fabric
Logic elements 573 thousand to 2.7 million 1.9 million to 4 million 3.2 million to 3.9 million
On-chip RAM MLAB, M20K, and eSRAM MLAB, M20K, and eSRAM MLAB and M20K
287 Mb 431 Mb 370 Mb
Variable precision DSP Industry-leading digital signal processing (DSP) support with up to 38 TFLOPS
Clocking and PLL
  • Programmable clock tree synthesis for flexible, low power, and low skew clocking
  • I/O PLL supports integer mode with precise frequency synthesis for general purpose I/O, external memory interfaces, LVDS, and fabric usage
  • Transmit PLL (TX PLL) supports fractional synthesis and ultra-low jitter with LC tank-based PLL for transceiver usage.
General purpose I/Os 1.2 V to 1.5 V general-purpose I/O (GPIO) 1.2 V to 1.5 V GPIO 1.05 V to 1.3 V GPIO
External memory interface Fourth generation scalable integrated hard memory controllers and PHY
3,200 Mbps DDR4 3,200 Mbps DDR4
  • 820 Gbps with HBM2E
  • 5,600 Mbps DDR5
  • 3,200 Mbps DDR4
  • 5,500 Mbps LPDDR5
  • Hardened memory NoC
HBM2E — — Yes
Memory NoC — — Yes
Cryptography High-performance hard crypto blocks1 supporting Advanced Encryption Standard (AES) and SM4 encryption standards High-performance hard crypto blocks1 supporting AES and SM4 encryption standards SDM supports AES
Transceiver hard IPs
  • Multiple Gigabit Ethernet (GbE) network interface connectivity in one device
  • PCS. PCIe* , and CXL* 2 hard IPs free up valuable core logic resources, save power, and increase your productivity
  • Hardened 10, 25, 40, 50, 100, 200, and 400 GbE media access control (MAC), physical coding sublayer (PCS), and forward error correction (FEC) with IEEE 1588 support
  • GbE up to 58 Gbps PAM4 or 32 Gbps non-return-to-zero (NRZ)
  • PCIe* 4.0 ×16
  • GbE up to 116 Gbps PAM4
  • Up to 4 Tbps of transceiver bandwidth
  • PCIe* 5.02 ×16 at 32 Gbps data rate
  • CXL* support2
  • GbE Up to 116 Gbps PAM4 or 58 Gbps NRZ
  • PCIe* 5.02 ×16 at 32 Gbps data rate
  • CXL* support2
SDM

Dedicated secure device manager (SDM) that:

  • Manages FPGA configuration process and all security features
  • Performs authenticated FPGA configuration and HPS boot
  • Supports FPGA bitstream encryption, secure key provisioning, and physically unclonable function (PUF) key storage
  • Manages runtime sensors and supports active tamper detection and responses
  • Supports platform attestation using the security protocol and data model (SPDM) protocol
  • Provides access to hardened cryptographic engines as a service
HPS

(SoCs only)

 Hard processor system (HPS) with embedded quad-core 64-bit Arm* Cortex* -A53 up to 1.4 GHz 3 processors
Power saving Comprehensive set of advanced power saving features that deliver up to 40% lower power compared to previous generation high-performance FPGAs
1 Only available in select devices. Refer to the family plan.
2 CXL* is available only for I-Series and M-Series FPGAs with at least one R-Tile.
3 Except AGI 035 and AGI 040 devices.
Level Two Title