Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.1. Key Features and Innovations in Intel® Agilex™ FPGAs and SoCs

With the power and performance efficiency of industry-leading 10-nm SuperFin and Intel® 7 technologies, the Intel® Agilex™ FPGA and SoC device family is available in several variants.
Table 1.  Variants of the Intel® Agilex™ FPGAs and SoCs
Features and Innovations Intel® Agilex™ Device Variants
D-Series F-Series I-Series M-Series
Application optimization For midrange FPGA applications requiring lower power and smaller form factor. For applications requiring an optimal balance of power and performance For high performance processor interface and bandwidth-intensive applications For compute-intensive, high-memory bandwidth applications
Process technology Intel® 7 Intel® 10-nm SuperFin Intel® 10-nm SuperFin Intel® 7
Architecture Monolithic die Chiplet architecture Chiplet architecture Chiplet architecture
Packaging "Balls anywhere" for smaller form factor and reduced number of PCB layers Rectangular package and hex pattern ball array for more functionality per area Rectangular package and hex pattern ball array for more functionality per area Rectangular package and hex pattern ball array for more functionality per area
Core fabric Second generation Intel® Hyperflex™ core fabric
Logic elements 103 thousand to 644 thousand 573 thousand to 2.7 million 1.9 million to 4 million 3.2 million to 3.9 million
On-chip RAM MLAB and M20K MLAB, M20K, and eSRAM MLAB, M20K, and eSRAM MLAB and M20K
38 Mb 287 Mb 431 Mb 370 Mb
Variable precision DSP Industry-leading digital signal processing (DSP) support with up to 38 TFLOPS
AI Tensor block Yes
Clocking and PLL
  • Programmable clock tree synthesis for flexible, low power, and low skew clocking
  • I/O PLL supports integer mode with precise frequency synthesis for general purpose I/O, external memory interfaces, LVDS, and fabric usage
  • Transmit PLL (TX PLL) supports fractional synthesis and ultra-low jitter with LC tank-based PLL for transceiver usage.
I/Os
  • 1.05 V to 1.3 V high-speed I/O (HSIO)
  • 1.8 V to 3.3 V high-voltage I/O (HVIO)
1.2 V to 1.5 V general-purpose I/O (GPIO) 1.2 V to 1.5 V GPIO) 1.05 V to 1.3 V GPIO
MIPI* D-PHY* v2.5 Up to 3.5 Gbps 5 per lane
External memory interface Fourth generation scalable integrated hard memory controllers and PHY
  • 4,000 Mbps DDR5
  • 3,200 Mbps DDR4
  • 4,267 Mbps LPDDR4 and LPDDR5
3,200 Mbps DDR4 3,200 Mbps DDR4
  • 820 Gbps with HBM2E
  • 5,600 Mbps DDR5
  • 3,200 Mbps DDR4
  • 5,500 Mbps LPDDR5
  • Hardened memory NoC
HBM2E Yes
Memory NoC Yes
Cryptography SDM supports Advanced Encryption Standard (AES) High-performance hard crypto blocks4 supporting AES and SM4 encryption standards High-performance hard crypto blocks4 supporting AES and SM4 encryption standards SDM supports AES
Transceiver hard IPs
  • Multiple Gigabit Ethernet (GbE) network interface connectivity in one device
  • PCS. PCIe* , and CXL* 3 hard IPs free up valuable core logic resources, save power, and increase your productivity
  • Hardened 10 and 25 GbE media access control (MAC), physical coding sublayer (PCS), and forward error correction (FEC) with IEEE 1588 support
  • GbE up to 28.1 Gbps non-return-to-zero (NRZ)
  • Up to PCIe* 4.0 ×8
  • Hardened 10, 25, 40, 50, 100, 200, and 400 GbE MAC, PCS, and FEC with IEEE 1588 support
  • GbE up to 58 Gbps PAM4 or 32 Gbps NRZ
  • PCIe* 4.0 ×16
  • Hardened 10, 25, 40, 50, 100, 200, and 400 GbE MAC, PCS, and FEC with IEEE 1588 support
  • GbE up to 116 Gbps PAM4
  • Up to 4 Tbps of transceiver bandwidth
  • PCIe* 5.03 ×16 at 32 Gbps data rate
  • CXL* support3
  • Hardened 10, 25, 40, 50, 100, 200, and 400 GbE MAC, PCS, and FEC with IEEE 1588 support
  • GbE Up to 116 Gbps PAM4 or 58 Gbps NRZ
  • PCIe* 5.03 ×16 at 32 Gbps data rate
  • CXL* support3
SDM

Dedicated secure device manager (SDM) that:

  • Manages FPGA configuration process and all security features
  • Performs authenticated FPGA configuration and HPS boot
  • Supports FPGA bitstream encryption, secure key provisioning, and physically unclonable function (PUF) key storage
  • Manages runtime sensors and supports active tamper detection and responses
  • Supports platform attestation using the security protocol and data model (SPDM) protocol
  • Provides access to hardened cryptographic engines as a service
HPS

(SoCs only)

Hard processor system (HPS) with embedded multicore Arm* processors
  • Dual-core 64-bit Arm* Cortex* -A76 up to 1.8 GHz
  • Dual-core 64-bit Arm* Cortex* -A55 up to 1.5 GHz
Quad-core 64-bit Arm* Cortex* -A53 up to 1.4 GHz 6 Quad-core 64-bit Arm* Cortex* -A53 up to 1.4 GHz 6 Quad-core 64-bit Arm* Cortex* -A53 up to 1.4 GHz 6
Power saving Comprehensive set of advanced power saving features that deliver up to 40% lower power compared to previous generation high-performance FPGAs
3 CXL* is available only for Intel® Agilex™ I-Series and M-Series devices with at least one R-Tile.
4 Only available in select devices. Refer to the family plan.
5 Up to 3.5 Gbps for standard reference channel, and up to 2.5 Gbps for long reference channel.
6 Except AGI 035 and AGI 040 devices.

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