Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs

The M20K and MLAB embedded memory blocks in Intel® Agilex™ FPGAs and SoCs are similar to the embedded memory of previous Intel® FPGA device families. Additionally, some Intel® Agilex™ devices feature eSRAM blocks with stitching support.
Table 24.  Embedded Memory Block Types and Features for Intel® Agilex™ FPGAs and SoCs
Feature MLAB M20K eSRAM39
Usage For wide and shallow memory configurations For supporting larger memory configurations For large memory configurations with fast path, low latency, and high bandwidth on-chip memory
Block size 640 bits 20 kilobits 18 Megabits
Configurations
  • 64×10 (emulated)
  • 32×20
  • 2,048×10 (or ×8)
  • 1,024×20 (or ×16)
  • 512×40 (or ×32)
  • 8 channels of 2.25 Mb (18 Mb)
  • Each channel contains 32 banks of 72×1K memory
Hard ECC Yes Yes
Modes Single-port RAM, dual-port RAM, FIFO, ROM, and shift register
39 Available in Intel® Agilex™ F-Series and I-Series devices.

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