Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs

All Intel® Agilex™ FPGAs and SoCs contain an SDM. The SDM is a triple-redundant processor that serves as the point of entry into the device for all JTAG and configuration commands. Additionally, the SDM in the Intel® Agilex™ FPGAs and SoCs enables system certification to FIPS140-3 layer 2 compliance.

The SDM bootstraps the HPS in Intel® Agilex™ SoCs. This bootstrapping ensures that the HPS boots using the same security features available to the FPGA.

Figure 21. SDM Block Diagram

During configuration, the Intel® Agilex™ FPGA or SoC divides into logical sectors. A local sector manager (LSM) manages each logical sector. The SDM passes configuration data to each LSMs across the on-chip configuration network.

Advantages of the sector-based approach:

  • Enables independent configuration of the sectors—one at a time or in parallel
  • Achieves simplified sector configuration and reconfiguration
  • Reduces overall configuration time caused by inherent parallelism.

The Intel® Agilex™ FPGAs and SoCs use the same sector-based approach to respond to SEUs and security attacks

Although the sectors provide a logical separation for device configuration and reconfiguration, the sectors overlay the normal rows and columns of FPGA logic and routing:

  • No impact to the Intel® Quartus® Prime software place and route
  • No impact to the timing of logic signals that cross the sector boundaries

The SDM enables robust, secure, and fully-authenticated device configuration. Additionally, the SDM allows you to customize the configuration scheme, enhancing device security.

Advantages of the SDM-based device configuration approach:

  • Provides a dedicated secure configuration manager
  • Reduces device configuration time because sectors are configured in parallel
  • Enables an updatable configuration process
  • Supports partial reconfiguration
  • Allows remote system update
  • Supports zeroization of whole device or individual sectors
Table 41.  Supported Configuration Schemes for Intel® Agilex™ FPGAs
Configuration Scheme Device Series Data Width Maximum Data Rate
Active Serial (AS) normal and fast modes All 4 bits 4 bits × 166 MHz = 664 Mbps
Avalon® streaming interface ×32

F-Series

I-Series

M-Series

32 bits 32 bits × 125 MHz = 4 Gbps
Avalon® streaming interface ×16

All

16 bits 16 bits × 125 MHz = 2 Gbps
Avalon® streaming interface ×8 All 8 bits 8 bits × 125 MHz = 1 Gbps
JTAG

All

1 bit 1 bit × 30 MHz = 30 Mbps
Configuration via Protocol (CvP)

F-Series

I-Series

M-Series

×8 and ×16 lanes

The maximum data rate depends on the PCIe* generation and number of lanes. Typically, the configuration data width is limited by the data rate of the device's internal configuration data path instead of the PCIe* link width.

D-Series

×1, ×2, ×4 and ×8 lanes
Applicable to the Intel® Agilex™ AGF 019, AGF 023, AGI 019, AGI 023, AGI 035, AGI 040, AGM 032, and AGM 039 devices.

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