18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs
The SDM bootstraps the HPS in Intel® Agilex™ SoCs. This bootstrapping ensures that the HPS boots using the same security features available to the FPGA.
During configuration, the Intel® Agilex™ FPGA or SoC divides into logical sectors. A local sector manager (LSM) manages each logical sector. The SDM passes configuration data to each LSMs across the on-chip configuration network.
Advantages of the sector-based approach:
- Enables independent configuration of the sectors—one at a time or in parallel
- Achieves simplified sector configuration and reconfiguration
- Reduces overall configuration time caused by inherent parallelism.
The Intel® Agilex™ FPGAs and SoCs use the same sector-based approach to respond to SEUs and security attacks
Although the sectors provide a logical separation for device configuration and reconfiguration, the sectors overlay the normal rows and columns of FPGA logic and routing:
- No impact to the Intel® Quartus® Prime software place and route
- No impact to the timing of logic signals that cross the sector boundaries
The SDM enables robust, secure, and fully-authenticated device configuration. Additionally, the SDM allows you to customize the configuration scheme, enhancing device security.
Advantages of the SDM-based device configuration approach:
- Provides a dedicated secure configuration manager
- Reduces device configuration time because sectors are configured in parallel
- Enables an updatable configuration process
- Supports partial reconfiguration
- Allows remote system update
- Supports zeroization of whole device or individual sectors
|Configuration Scheme||Device Series||Data Width||Maximum Data Rate|
|Active Serial (AS) normal and fast modes||All||4 bits||4 bits × 166 MHz = 664 Mbps|
|Avalon® streaming interface ×32||
|32 bits||32 bits × 125 MHz = 4 Gbps|
|Avalon® streaming interface ×16||
|16 bits||16 bits × 125 MHz = 2 Gbps|
|Avalon® streaming interface ×8||All||8 bits||8 bits × 125 MHz = 1 Gbps|
|1 bit||1 bit × 30 MHz = 30 Mbps|
|Configuration via Protocol (CvP)||
|×8 and ×16 lanes||
The maximum data rate depends on the PCIe* generation and number of lanes. Typically, the configuration data width is limited by the data rate of the device's internal configuration data path instead of the PCIe* link width.
|×1, ×2, ×4 and ×8 lanes|
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