Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

11. Hard Processor System in Intel® Agilex™ SoCs

The Intel® Agilex™ SoCs hard processor system (HPS) consists of multicore Arm* processors. Additionally, the HPS adds a system memory management unit that enables system-wide hardware virtualization.

With the HPS architecture improvements, the Intel® Agilex™ SoCs fulfill the requirements of current and future embedded markets, including:

  • Wireless and wireline communications
  • Datacenter acceleration
  • Numerous military applications
  • Various industrial applications

The HPS of the Intel® Agilex™ F-Series, I-Series, and M-Series SoCs consists a quad-core Arm* Cortex* -A53, allowing you to easily migrate existing SoC designs from Intel® Stratix® 10 SoCs. The HPS of the Intel® Agilex™ D-Series SoCs consists of a dual-core Arm* Cortex* -A76 and a dual-core Arm* Cortex* -A55 processors.

Figure 14. HPS Block Diagram— Intel® Agilex™ F-Series, I-Series, and M-Series SoCs


Figure 15. HPS Block Diagram— Intel® Agilex™ D-Series SoCs


Table 32.  Summary of Intel® Agilex™ SoCs Key Features
Feature Series Description
Processor units All
  • Run 64-bit and 32-bit Arm* instructions
  • 16-bit and 32-bit Thumb instructions for 30% reduction in memory footprint
  • Arm* Jazelle* runtime compilation target (RCT) execution architecture with 8-bit Java* bytecodes
  • Superscalar, variable-length, out-of-order pipeline with dynamic branch prediction
  • Improved Arm* Neon* media processing engine
  • Single-precision and double-precision floating-point unit
  • Arm* CoreSight* debug and trace technology

F-Series

I-Series

M-Series

Quad-core Arm* Cortex* -A53 MPCore* processor unit.
  • CPU frequency up to 1.4 GHz
    • 2.3 MIPS/MHz instruction efficiency
    • At 1.4 GHz, total performance of 13,800 MIPS
  • Arm* v8-A architecture
D-Series Multicore of dual-core Arm* Cortex* -A76 MPCore* and dual-core Arm* Cortex* -A55 MPCore* processor units.
  • CPU frequency:
    • Dual-core Arm* Cortex* -A76—up to 1.8 GHz
    • Dual-core Arm* Cortex* -A55—up to 1.5 GHz
  • Arm* v8.2-A architecture
System memory management unit All
  • Enables a unified memory model
  • Extends hardware virtualization into peripherals implemented in the FPGA fabric
Cache coherency unit All Propagates changes in shared data stored in cache throughout the system to provide I/O coherency for co-processing elements
Cache memory

F-Series

I-Series

M-Series

Quad-core Arm* Cortex* -A53
  • L1 cache:
    • 32 KB L1 I-cache with parity check
    • 32 KB of L1 D-cache with ECC
    • Parity checking
  • L2 cache:
    • Shared 1 MB
    • 8-way set associative
    • SEU protection with parity on TAG ram and ECC on data RAM
    • Cache lockdown support
D-Series Common Shared 2 MB L3 cache
Dual-core Arm* Cortex* -A76
  • 64 KB L1 I-cache and 64 KB L1 D-cache with ECC per core
  • 256 KB shared L2 cache
Dual-core Arm* Cortex* -A55
  • 32 KB L1 I-cache and 32 KB L1 D-cache with ECC per core
  • 128 KB shared L2 cache
On-chip memory

F-Series

I-Series

M-Series

256 KB on-chip RAM
D-Series 512 KB on-chip RAM
External SDRAM and flash memory Interfaces for HPS Hard memory controller All
  • 40-bit (32-bit + 8-bit ECC)
  • ECC support including calculation, error correction, write-back correction, and error counters
  • Software-configurable priority scheduling on individual SDRAM bursts
  • Fully programmable timing parameter support for all JEDEC* -specified timing parameters
  • Multi-port front end (MPFE) interface to the hard memory controller, supporting AMBA* 4 AXI QoS for interface to the FPGA fabric

F-Series

I-Series

M-Series

  • Supports DDR4, up to 3200 Mbps
  • Some packages support 72-bit (64 bit + 8 bit ECC)
D-Series
  • Supports DDR4, DDR5, LPDDR4, and LPDDR5
NAND flash controller All
  • Integrated descriptor-based controller with DMA
  • Programmable hardware ECC support
  • Support for 8-bit and 16-bit flash devices

F-Series

I-Series

M-Series

Supports the ONFI 1.0 specification
D-Series
  • Compatible with the ONFI 1.x, 2.x, 3.x, and 4.1 specifications
  • Compatible with Toggle 1.x and 2.x specifications
SD/SDIO/MMC controller All
  • Integrated descriptor-based DMA controller
  • Supports CE-ATA digital commands

F-Series

I-Series

M-Series

  • Supports eMMC version 4.5
  • 50 MHz operating frequency
D-Series
  • Supports SD devices up to version 6.1
  • Supports SDIO devices up to version 4.1
  • Supports SD/eMMC devices up to version 5.1
  • Supports SD SDR12, SDR25, SDR50, SDR104, and DDR50
  • Supports eMMC legacy, high-speed SDR, high-speed DDR, HS200, and HS400
  • Does not support UHS-II and UHS-III interfaces
DMA controller

F-Series

I-Series

M-Series

  • Eight channels
  • Supports up to 32 peripheral handshake interfaces
D-Series
  • Two controllers with four channels each
  • Supports up to 48 peripheral handshake interfaces
Communication interface controllers Ethernet MAC

F-Series

I-Series

M-Series

  • Three Ethernet MACs supporting 10 Mbps, 100 Mbps, and 1 Gbps with integrated DMA
  • Ethernet standards:
    • IEEE 1588-2002 and IEEE 1588-2008 standards for precise networked clock synchronization
    • IEEE 802.1Q VLAN tag detection for reception frames
    • Ethernet AVB
  • Ethernet interfaces:
    • Supports RGMII and RMII external PHY Interfaces
    • Supports MII and GMII operating modes through standard FPGA I/O
    • Supports RMII operating mode using MII to RMII adapter
    • Supports RGMII operating mode using GMII to RGMII adapter
    • Supports SGMII operating mode using GMII to SGMII adapter
D-Series
  • Three Ethernet MACs supporting 10 Mbps, 100 Mbps, 1 Gbps, and 2.5 Gbps with integrated DMA and TSN support
  • Ethernet standards with TSN endpoint functionality compliant to:
    • IEEE 1588-2008 advanced timestamps: Precision Time Protocol (PTP) for precise networked clock synchronization
    • IEEE 802.1AS-2011: Timing and synchronization
    • IEEE 802.1Qav-2009: Forwarding and queuing for time-sensitive streams
    • IEEE 802.1Qbv-2015: Time-scheduled traffic enhancements
    • IEEE 802.3br-2015 and IEEE 802.1Qbu-2016: Pre-emption
    • IEEE 802.1Q: VLAN and stack VLAN support
    • IEEE 802.1AS-2011: Timing and synchronization for TSN
  • Ethernet interfaces:
    • Supports RGMII operating mode at 10 Mbps, 100 Mbps, and 1 Gbps data rates through HPS I/O
    • Supports MII, RMII, GMII, and RGMII operating modes at 10 Mbps, 100 Mbps, and 1 Gbps data rates through standard FPGA I/O (some interfaces require soft adapter in FPGA logic)
    • Supports SGMII operating mode at 1 Gbps (1000BASE-X) or 10 Mbps, 100 Mbps, and 1 Gbps (SGMII) data rates with SGMII PCS soft IP through TDS I/O
    • Supports SGMII+ operating mode at 10 Mbps, 100 Mbps, 1 Gbps, and 2.5 Gbps data rates with SGMII+ PCS soft IP and serial transceiver interface through FPGA I/O
USB 2.0 OTG All
  • Dual-role device (device and host functions)
    • High-speed (480 Mbps)
    • Full-speed (12 Mbps)
    • Low-speed (1.5 Mbps)
    • Supports USB 1.1 (full-speed and low-speed)
  • Integrated descriptor-based scatter-gather DMA
  • Support for external ULPI PHY
  • Up to 16 bidirectional endpoints, including control endpoint
  • Up to 16 host channels
  • Supports generic root hub
  • Configurable to USB OTG 1.3 and USB OTG 2.0 modes

F-Series

I-Series

M-Series

Two USB OTG controllers with DMA
D-Series One USB OTG controller
USB 3.1 Gen1 D-Series
  • Supports both device and host controller modes
    • Both USB 3.1 and USB 2.0 interfaces must be configured as device or host; mixing modes is not supported
  • Supports up to 5 Gbps if configured for USB 3.1 Gen1 and interfaced with the transceiver
  • Supports up to 480 Mbps if configured for USB 2.0 and interfaced with the HPS I/O
I2C All
  • Five I2C controllers, three can be used by the Ethernet MAC for MIO to external PHY
  • Support 100 Kbps and 400 Kbps modes
  • Support 7-bit and 10-bit addressing modes
  • Support master and slave operating modes
I3C D-Series
  • Two I3C controllers
    • One configured as the primary master
    • One configured as the secondary master
  • Supports FM, FM+, and SDR data rates up to 12.5 Mbps
UART All
  • Two UART 16550-compatible controllers
  • Programmable baud rate up to 115.2 kilobaud
SPI All
  • Four SPI (two masters, two slaves)
  • Supports full duplex and half duplex
Timers All Four general-purpose timers

F-Series

I-Series

M-Series

Four watchdog timers
D-Series Five watchdog timers
I/O All
  • 48 HPS direct I/Os allow HPS peripherals to connect directly to the I/Os
  • Up to two FPGA fabric I/O banks assignable to the HPS for HPS DDR access
Interconnect to logic core HPS–to–FPGA bridge All
  • Allows HPS bus masters to access bus slaves in FPGA fabric
  • Configurable 32-, 64-, or 128-bit AMBA* AXI data interface allows high-bandwidth HPS master transactions to FPGA fabric
D-Series Supports up to 256 gigabytes (GB) of address space
HPS–to–SDM and SDM–to–HPS bridges

F-Series

I-Series

M-Series

Allows the HPS to reach the SDM block and the SDM to bootstrap the HPS
Lightweight HPS–to–FPGA bridge All Lightweight 32-bit AMBA* AXI interface suitable for low bandwidth register access from HPS to soft peripherals in the FPGA fabric
D-Series Supports up to 512 MB of address space
FPGA–to–HPS bridge

F-Series

I-Series

M-Series

  • Configurable 128, 256, or 512 bits ACE-Lite interface
  • Up to 256-bit FPGA–to–HPS interface targeting the HPS
  • Up to 512-bit FPGA–to–HPS interface targeting the DDR
D-Series
  • 256 bits FPGA–to–HPS interface targeting the HPS peripherals and shared SDRAM
  • Shared SDRAM accessible using non-coherent46 or hardware-supported I/O coherent transactions
  • Supports ACE5-Lite cache stashing into L3 cache of the DynamIQ Shared Unit or L1 cache of individual core
FPGA–to–SDRAM bridge D-Series
  • 64, 128, or 256 bits FPGA–to–SDRAM interface targeting the DDR I/O
  • Supports only non-coherent46 transactions
46 For non-coherent transactions, ensure that the HPS and FPGA soft logic do not interfere in each other's SDRAM space.

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