Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 4/01/2024
Document Table of Contents

13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series

Agilex™ 7 FPGAs and SoCs M-Series offer options for integrated HBM2E DRAM memory. The HBM2E memory blocks are inside the package together with the high-performance FPGA core fabric, transceiver tiles, and HPS.

The in-package inclusion of the HBM2E memory results in a near-memory compute implementation that allows up to 820 GBps total aggregate memory bandwidth. This aggregate bandwidth is an increase of over ten times compared to DDR5 memory bandwidth. A near-memory configuration also reduces system power by reducing traces between the FPGA and memory, while also reducing board area.

Some M-Series FPGAs have two integrated HBM2E DRAM memory stacks inside the package. Each DRAM stack contains:

  • 8 GB or 16 GB density per stack with 16 GB or 32 GB total density per device
  • 410 GBps memory bandwidth per stack with 820 GBps total aggregate memory bandwidth per device
  • Eight 128-bits wide independent channels or sixteen 64-bits wide independent pseudo channels
  • Data transfer rates of up to 3.2 Gbps per signal between the core fabric and the HBM2E DRAM memory

The core fabric of the M-Series FPGAs can interface with the HBM2E directly or through the hardened memory NoC.