Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs

Intel® Agilex™ M-Series devices offer options for integrated HBM2E DRAM memory. The HBM2E memory blocks are inside the package together with the high-performance FPGA core fabric, transceiver tiles, and HPS.

The in-package inclusion of the HBM2E memory results in a near-memory compute implementation that allows up to 820 GBps total aggregate memory bandwidth. This aggregate bandwidth is over ten times increase in compared to DDR5 memory bandwidth. A near-memory configuration also reduces system power by reducing traces between the FPGA and memory, while also reducing board area.

Some Intel® Agilex™ M-Series devices have two integrated HBM2E DRAM memory stacks inside the package. Each DRAM stack contains:

  • 8 GB or 16 GB density per stack with 16 GB or 32 GB total density per device
  • 410 GBps memory bandwidth per stack with 820 GBps total aggregate memory bandwidth per device
  • Eight 128-bits wide independent channels or 16 64-bits wide independent pseudo channels
  • Data transfer rates of up to 3.2 Gbps per signal between the core fabric and the HBM2E DRAM memory

The core fabric of the Intel® Agilex™ M-Series devices can interface with the HBM2E directly or through the hardened memory NoC.

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