Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/31/2023
Document Table of Contents

1.4. Additional Features for Intel Agilex® 7 SoCs

In addition to the common features of Intel Agilex® 7 devices, the Intel Agilex® 7 SoCs provide additional features.
Table 3.  Features Specific to Intel Agilex® 7 SoCs
SoC Subsystem Feature Description
HPS Multiprocessor unit core
  • Quad-core Arm* Cortex* -A53 MPCore* processor with Arm* CoreSight* debug and trace technology
  • Scalar floating-point unit supporting single and double precision
  • Arm* Neon* media processing engine for each processor
System controllers
  • System memory management unit (SMMU)
  • Cache coherency unit (CCU)
  • Arm* Cortex* -A53:
    • Level 1 cache per core:
      • 32 kilobytes (KB) L1 instruction cache with parity
      • 32 KB L1 data cache with ECC
  • 1 megabyte (MB) shared L2 cache with ECC
On-chip memory 256 KB on-chip RAM
Direct memory access (DMA) Eight-channel DMA controller
Ethernet XGMAC (TSN)
  • Three 10 Mbps/100 Mbps/1 Gbps/2.5 Gbps Ethernet XGMAC with integrated DMA and Time-Sensitive Networking (TSN) support
  • 1 Gbps and 2.5 Gbps (2.5 Gbps requires soft paths to transceivers)
USB Two USB 2.0 On-The-Go (OTG) with integrated DMA
UART Two UART 16550-compatible controllers
Serial peripheral interface (SPI) controller Four SPI (two masters and two slaves)
I2C Five I2C controllers
SD/SDIO/MMC controller
  • One eMMC version 4.5 with DMA and CE-ATA support
  • SD, including eSD, version 3.0
  • SDIO, including eSDIO, version 3.0
  • CE-ATA version 1.1
NAND flash controller
  • One ONFI 1.0
  • 8 bit and 16 bit support
GPIO Maximum of 48 software-programmable GPIOs
  • Four general-purpose timers
  • Four watchdog timers
  • Secure boot
  • AES encryption
  • Secure Hash Algorithms (SHA) and Elliptic Curve Digital Signature Algorithm (ECDSA) authentications
External memory interface

Hard memory controllers:

  • F-Series and I-Series—DDR4
  • M-Series—DDR4, DDR5, and LPDDR5