12.2.2. PCS Features in Intel® Agilex™ D-Series Transceivers
The PCS contains multiple gearbox implementations to decouple the PMA and PCS interface widths. The transceiver (PMA with optional FEC or PCS) to FPGA fabric interface support from 8 bits up to 66 bits options. This feature allows you to implement a wide range of applications.
The PCS hard IP supports various standard and proprietary protocols across a wide range of data rates and encoding schemes.
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