Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 4/01/2024
Document Table of Contents

12.2.3. Transceiver PLL in Intel® Agilex™ D-Series FPGAs and SoCs

There are two types of PLL in the Intel® Agilex™ D-Series transceiver.
Table 39.  Types of Intel® Agilex™ D-Series Transceiver PLL
PLL Type Description
  • Four TX PLL per bank or one TX PLL per transceiver channel
  • LC tank-based PLL with precise fractional synthesis and ultra-low jitter
  • Supports transceiver interfaces
  • Dedicated for transceiver usage
System PLL
  • One System PLL per bank
  • Supports only integer mode with precise frequency synthesis
  • Supports transceiver-to-fabric interfaces
  • If not used for transceivers, you can repurpose the System PLL for core fabric usage