Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

2.1. Power Rail Sequence Grouping in Power-Up Sequence (PUS)

In order to simplify the power sequencing of the FPGA, the voltage rails are divided into 3 groups as shown in the . The voltage rails of the lowest group comes up first in the PUS and go down last in the power-down sequence (PDS). Voltage rails in Group 1 comes up first, followed by Group 2, and then Group 3 in the PUS. Voltage rails in Group 3 comes down first, followed by Group 2, and then Group 1 in the PDS. All the voltage rails within each group are enabled and disabled at the same time.

shows the Intel® Agilex™ device family power rail grouping and the required PUS covering for both ES and production devices.

Table 1.   Intel® Agilex™ Device Power Rail Grouping for the PUS Purpose
Power Group FPGA Core and Hard Processor System (HPS) Additional Voltage Rails
E-Tile P-Tile F-Tile R-Tile
Group 1

VCC

VCCP

VCCH

VCCL_SDM

VCCH_SDM

VCCPLLDIG_SDM

VCCL_HPS

VCCPLLDIG_HPS

VCCRT_GXE

VCC_HSSI_GXE

VCCRTPLL_GXE

VCC_HSSI_GXP

VCCRT_GXP

VCCFUSE_GXP

VCC_HSSI_GXF

VCCERT_FGT_GXF

VCCERT1_FHT_GXF

VCCERT2_FHT_GXF

VCC_HSSI_GXR

VCCE_PLL_GXR

VCCRT_GXR

VCCE_DTS_GXR

Group 2

VCCPT

VCCPLL_SDM

VCCADC

VCCPLL_HPS

VCCA_PLL 1

VCCH_GXE

VCCCLK_GXE

VCCH_GXP

VCCCLK_GXP

VCCFUSEWR_GXF

VCCCLK_GXF

VCCH_FGT_GXF

VCCEHT_FHT_GXF

VCCFUSECORE_GXF

VCCED_GXR

VCCCLK_GXR

VCCHFUSE_GXR

VCCH_GXR

Group 3

VCCA_PLL 2

VCCR_CORE

VCCIO_PIO_SDM

VCCIO_PIO

VCCFUSEWR_SDM

VCCIO_SDM

VCCIO_HPS

— — — —

The following lists the summary of the Intel® Agilex™ device family required PUS:

  • PUS is a requirement, not a recommendation
  • PUS must be a controlled event (Group 1 > Group 2 > Group 3)
  • HBM PUS and PDS is defined by the JEDEC specification
  • VCCBAT can be powered up at any time
  • Configuration via Protocol (CvP) or autonomous hard IPs (HIPs) must be within 10 ms from the first power supply ramp up to the last power supply ramp up
  • All voltage rails must ramp up monotonically
  • All voltage rails must ramp up to the full tRAMP specification (as stated in the device data sheet)
  • Do not drive I/O pins during a PUS

For more information, refer to the Power-Up Sequence Requirements section in the Intel® Agilex™ Power Management User Guide.

1 For AGF014 2486A Early Silicon.
2 For AGF014 2486A production silicon.
Level Two Title