Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

2.4.1. Intel® Agilex™ AGF012/AGF014, Intel® Agilex™ AGI027/AGI023/AGI022, and Intel® Agilex™ AGF027/AGF023/AGF022 FPGA Packages Board-Level Decoupling Capacitors Summary

Table 9 shows the PCB recommended FPGA decoupling capacitor requirement for the Intel® Agilex™ AGF012/AGF014 (medium package size), Intel® Agilex™ AGI027/AGI023/AGI022, and Intel® Agilex™ AGF027/AGF023/AGF022 large device packages.

Fabric or core decoupling capacitors are highly dependent on the size of the core or fabric (LE and number of GPIO pins) in the package. Intel® plans to add more packages to Table 9 in the future release to address decoupling capacitors solutions for other Intel® Agilex™ devices.

To address PCB decoupling capacitors for other packages, you can also use the recommended AGF012/AGF014 decoupling capacitors in Table 9 for the AGF006/AGF008 device packages. The AGF006/AGF008 device packages have the smallest fabric/core in the Intel® Agilex™ device family compared to the AGF012/AGF014 devices with medium core/fabric size. For that reason, adopting the AGF012/AGF014 decoupling capacitors for the AGF006/AGF008 devices might be slightly over designing, but highly recommended until we address more packages in Table 9 in the future release. For the same reason, you can also implement the AGF027/AGF023/AGF022/AGI027/AGI023/AGI022 decoupling capacitors (addressing the large core/fabric packages) in Table 9 for the AGF019/AGI019 device packages.

Decoupling capacitor recommendations for each tile is valid for any size of packages.

Table 9.   Intel® Agilex™ AGF012/AGF014, Intel® Agilex™ AGI027/AGI023/AGI022, and Intel® Agilex™ AGF027/AGF023/AGF022 FPGA Decoupling Capacitors Summary
System Intel® Agilex™ Power and Thermal Calculator (PTC) Rail Name Bottom-side Capacitors FPGA Periphery Capacitors Notes
Thick PCB (>65 mil thickness) Thin PCB (≤65 mil thickness) Thick PCB (>65 mil thickness) Thin PCB (≤65 mil thickness)
FPGA/PIO AGF012/AGF014 VCC

9x 47uF 0805

30x 10uF 0402 DNI 7

5x 47uF 0805

30x 10uF 0402 DNI7

6x 47uF 0805

 3x 47uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (47uF) capacitors inside bottom-side cavity.

Use 47uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.
FPGA/PIO AGF012/AGF014 VCCP
FPGA/PIO AGF019/AGF023 and AGI029/AGI023 VCC

4x 100uF 0805

4x 47uF 0805

20x 10uF 0402 DNI7

6x 100uF 0805

6x 47uF 0805

30x 10uF 0402 DNI7

4x 100uF 0805

4x 47uF 0805

6x 100uF 0805

6x 47uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (47uF and 100uF) capacitors inside bottom-side cavity.

Use 47uF and 100uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.
FPGA/PIO AGF019/AGF023 and AGI029/AGI023 VCCP
FPGA/PIO AGF022/AGF027 and AGI022/AGI027 VCC

6x 100uF 0805

4x 47uF 0805

30x 10uF 0402 DNI7

8x 100uF 0805

4x 47uF 0805

40x 10uF 0402 DNI7

10x 100uF 0805

8x 47uF 0805

12x 100uF 0805

10x 47uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (47uF and 100uF) capacitors inside bottom-side cavity.

Use 47uF and 100uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.
FPGA/PIO AGF022/AGF027 and AGI022/AGI027 VCCP
FPGA/HPS VCCPLLDIG_HPS 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA/HPS VCCL_HPS

2x 10uF 0402 or 3x 4.7uF 0201

2x 10uF 0402 or 3x 4.7uF 0201

1x 22uF 0603

1x 22uF 0603

 For SoC-centric designs.
FPGA VCCH

4x 22uF (0603 or 0402) or 9x 10uF 0402

4x 22uF (0603 or 0402) or 9x 10uF 0402

 2x 47uF 0805 2x 47uF 0805 Place thick 0603 (22uF) capacitors inside bottom-side cavity.
FPGA/SDM VCCH_SDM 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA/SDM VCCL_SDM 2x 1uF 0201 2x 1uF 0201 N/A N/A —
FPGA/SDM VCCPLLDIG_SDM 1x 1uF 0201 1x 1uF 0201 LC filter capacitors LC filter capacitors —
FPGA VCCPT 2x 4.7uF 0201 2x 4.7uF 0201 LC filter capacitors LC filter capacitors —
FPGA/PIO VCCRCORE 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA/PIO VCCA_PLL 2x 10uF 0402 2x 10uF 0402 LC filter capacitors LC filter capacitors —
FPGA/SDM VCCADC 1x 4.7uF 0402 or 0201 1x 4.7uF 0402 or 0201 LC filter capacitors LC filter capacitors —
FPGA/SDM VCCPLL_SDM 2x 4.7uF 0402 or 0201 2x 4.7uF 0402 or 0201 LC filter capacitors LC filter capacitors —
FPGA/HPS VCCPLL_HPS 2x 4.7uF 0402 or 0201 2x 4.7uF 0402 or 0201 LC filter capacitors LC filter capacitors —
FPGA/SDM VCCIO_PIO_SDM N/A N/A N/A N/A —
FPGA/PIO VCCIO_PIO 2x 4.7uF 0402 2x 4.7uF 0402 1x 10uF 0402 1x 10uF 0402 Per each I/O bank
FPGA/SDM VCCIO_SDM 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA/HPS VCCIO_HPS 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA/SDM VCCBAT 1x 47nF 0201 1x 47nF 0201 N/A N/A —
FPGA/SDM VCCFUSEWR_SDM 1x 1uF 0201 1x 1uF 0201 N/A N/A —
7 DNI: Do not install these capacitors but include the footprints of these capacitors. This is for defensive design for additional decoupling capacitance in the event the cavity capacitor (0805) is not sufficient.
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