25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683252
Date 6/18/2020
Public
Document Table of Contents

2.4.1. Testbench

Figure 10. Block Diagram of the 10G/25G Ethernet Single-Channel Design Example Simulation Testbench
Table 5.  Testbench Components
Component Description
Device under test (DUT) The 25G Ethernet Intel® FPGA IP core.
Reconfiguration Sequencer Reconfigures the transceiver channel speed from 10 Gbps to 25 Gbps, and vice versa.
Ethernet Packet Generator and Packet Monitor
  • Packet generator generates frames and transmit to the DUT.
  • Packet Monitor monitors TX and RX datapaths and displays the frames in the simulator console.
ATX PLL Generates a TX serial clock for the Intel® Stratix® 10 10G/25G transceiver which is wrapped in the 25G Ethernet Intel® FPGA IP core.
Note: For the 10G/25G Ethernet single-channel design example with IEEE 1588v2 feature simulation testbench, refer to Figure 7.

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