25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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2.3.1. Design Components

Table 4.  Design Components
Component Description
25G Ethernet Intel® FPGA IP

Consists of MAC, PCS, and Transceiver PHY, with the following configuration:

  • Core Variant: MAC+PCS+PMA, MAC+PCS
  • Enable flow control: Optional
  • Enable link fault generation: Optional
  • Enable preamble passthrough: Optional
  • Enable statistics collection: Optional
  • Enable MAC statistics counters: Optional
  • Enable 10G/25G dynamic rate switching: Selected
  • Enable Native PHY Debug Master Endpoint (NPDME): Optional
  • Reference clock frequency: 644.531250/322.265625
For the design example with the IEEE 1588 feature, the following additional parameters are configured:
  • Enable IEEE 1588: Selected
  • Time of day format: Enable 96-bit timestamp format 1
For the design example with the RS-FEC feature, the following additional parameter is configured:
  • Enable RS-FEC: Selected
Reconfiguration Sequencer Reconfigures the transceiver channel speed from 10 Gbps to 25 Gbps, and vice versa.
ATX PLL Generates TX serial clocks for the 10G and 25G transceivers.
Client logic Consists of:
  • Traffic generator, which generates burst packets to the 25G Ethernet Intel® FPGA IP core for transmission.
  • Traffic monitor, which receives burst packets from the 25G Ethernet Intel® FPGA IP core.
Source and Probe Source and probe signals, including system reset input signal, which you can use for debugging.
Design Components for the IEEE 1588v2 Feature
Sampling PLL Generates the clocks for the IEEE 1588v2 design components.
  • latency_sclk: 156.25 MHz for latency measurement.
  • sampling_clk: 250 MHz for ToD synchronization
Time-of-day (ToD) Sync Synchronizes the 10G and 25G ToDs.
ToD Tx ToD for transmit paths for the 10G and 25G transceivers.
ToD Rx ToD for receive paths for the 10G and 25G transceivers.
Master Precision Time Protocol (PTP) Master PTP consists of a packet generator and a packet receiver.
  • Packet generator: Obtains timestamp information from the 25G Ethernet Intel® FPGA IP core and generates Avalon® streaming packets such as Sync packet and Delay Response packet.
  • Packet receiver: Obtains the delay request packet information from the 25G Ethernet Intel® FPGA IP core and produces timestamp values.
Slave PTP Slave PTP consists of a packet generator, a packet receiver, and packet compute.
  • Packet generator: Obtains timestamp information from the 25G Ethernet Intel® FPGA IP core and generates Avalon® streaming packets such as Delay Request packet.
  • Packet receiver: Obtains the Sync and Delay Response packets information from the 25G Ethernet Intel® FPGA IP core and produces timestamp values.
  • Packet compute: Calculates and produces the delay and offsets value based on the timestamp values.
1 The 10G/25G Ethernet single-channel design example with IEEE 1588v2 feature only supports 96-bit timestamp format.

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