1. 25G Ethernet Intel® FPGA IP Quick Start Guide 2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices 5. 25G Ethernet Intel® FPGA IP Design Example References 6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware
2.3.1. Design Components
|25G Ethernet Intel® FPGA IP||
Consists of MAC, PCS, and Transceiver PHY, with the following configuration:
For the design example with the IEEE 1588 feature, the following additional parameters are configured:
For the design example with the RS-FEC feature, the following additional parameter is configured:
|Reconfiguration Sequencer||Reconfigures the transceiver channel speed from 10 Gbps to 25 Gbps, and vice versa.|
|ATX PLL||Generates TX serial clocks for the 10G and 25G transceivers.|
|Client logic||Consists of:
|Source and Probe||Source and probe signals, including system reset input signal, which you can use for debugging.|
|Design Components for the IEEE 1588v2 Feature|
|Sampling PLL||Generates the clocks for the IEEE 1588v2 design components.
|Time-of-day (ToD) Sync||Synchronizes the 10G and 25G ToDs.|
|ToD Tx||ToD for transmit paths for the 10G and 25G transceivers.|
|ToD Rx||ToD for receive paths for the 10G and 25G transceivers.|
|Master Precision Time Protocol (PTP)||Master PTP consists of a packet generator and a packet receiver.
|Slave PTP||Slave PTP consists of a packet generator, a packet receiver, and packet compute.
1 The 10G/25G Ethernet single-channel design example with IEEE 1588v2 feature only supports 96-bit timestamp format.
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