25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature

Note: For 25G Ethernet single-channel design example with IEEE 1588v2 feature simulation testbench, refer to Figure 14.

The simulation test case performs the following actions:

  1. Instantiates , ATX PLL, and IO PLL (sampling PLL).
  2. Waits for RX clock and PHY status signal to settle.
  3. Prints PHY status.
  4. Checks for 10 valid data.
  5. Analyzes the results. The successful testbench displays "Testbench complete." when the PTP delay and offset data are within the threshold values.

The following sample output illustrates a successful simulation test run:

# 
# Waiting for RX alignment...
# iatpg_pipeline_global_en is set
# iatpg_pipeline_global_en is set
# RX deskew locked.
# RX lane aligmnent locked.
# 
# Sending packets...
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064457
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064bb4
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000fffffffff8a2
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000643b5
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000520
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000634fb
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063f3b
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063a1a
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x00000000000000000006445a
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063e95
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000648d5
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000643b5
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000520
# Offset within tolerence range.
# 
# 
# 
# Finished sending packets.
# 
# **
# ** Testbench complete.
# **
Figure 19. Sample Simulation Output for Design Example with the IEEE 1588v2 Feature (Part 1 of 2)
Figure 20. Sample Simulation Output for Design Example with the IEEE 1588v2 Feature (Part 2 of 2)

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