25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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3.4.2. Simulation Design Example Components

Table 10.  25G Ethernet Single-Channel Design Example Testbench File Descriptions
File Name Description
Testbench and Simulation Files
basic_avl_tb_top.v Top-level testbench file. The testbench instantiates the DUT, performs Avalon® memory-mapped configuration on design components and client logic, and sends and receives packet to or from the 25G Ethernet Intel® FPGA IP.
Testbench Scripts
run_vsim.do The ModelSim script to run the testbench.
run_vcs.sh The Synopsys VCS* script to run the testbench.
run_ncsim.sh The Cadence NCSim script to run the testbench.
run_xcelium.sh The Xcelium* script to run the testbench.