25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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5.1. Design Example Interface Signals

The 25G Ethernet Intel® FPGA IP core testbench is self-contained and does not require you to drive any input signals.

Table 14.  Hardware Design Example Interface Signals for 25G Ethernet Intel® FPGA IP Core for Intel® Stratix® 10 Devices
Signal Direction Comments
clk100 Input

Drive at 100 MHz. The intent is to drive this from a 100 Mhz oscillator on the board.

clk_ref Input Drive at 644.53125 MHz or 322.265625 MHz from an oscillator on the board.
cpu_resetn Input Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.
tx_serial Output Transceiver PHY output serial data.
rx_serial Input Transceiver PHY input serial data.
user_led[7:0] Output Status signals. The hardware design example connects these bits to drive LEDs on the target board. Individual bits reflect the following signal values and clock behavior:
  • [0]: Main reset signal to IP core
  • [1]: Reserved
  • [2]: Divided version of clk50
  • [3]: Divided version of 100 MHz status clock
  • [4]: tx_lanes_stable
  • [5]: rx_block_lock
  • [6]: rx_am_lock
  • [7]: rx_pcs_ready