25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683252
Date 6/18/2020
Public
Document Table of Contents

2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices

The 10G/25G Ethernet single-channel design example demonstrates an Ethernet solution for Intel® Stratix® 10 devices using the 25G Ethernet Intel® FPGA IP core.

Generate the design example from the Example Design tab of the 25G Ethernet Intel® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. You can also choose to generate the design with or without the Reed-Solomon Forward Error Correction (RS-FEC) feature.

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