2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
Generate the design example from the Example Design tab of the 25G Ethernet Intel® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. You can also choose to generate the design with or without the Reed-Solomon Forward Error Correction (RS-FEC) feature.
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