25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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4.4.3. Test Case

The simulation test case performs the following steps:

  1. Instantiates 25G Ethernet Intel® FPGA IP and ATX PLL.
  2. Waits for PHY status signal to settle.
  3. Prints PHY status.
  4. Analyzes the results. The successful testbench sends and receives packets, and displays "Testbench complete."
Figure 23. Sample Simulation Output when Ethernet Channel is Configured to 1This figure shows a successful simulation test run when the Ethernet channel (i.e., LINK) is configured to 1.
Figure 24. Sample Simulation Output when Ethernet Channel is Configured to 4 (Part 1 of 2)This figure shows a successful simulation test run when the Ethernet channel (i.e., LINK) is configured to 4.
Figure 25. Sample Simulation Output when Ethernet Channel is Configured to 4 (Part 2 of 2)This figure shows a successful simulation test run when the Ethernet channel (i.e., LINK) is configured to 4.

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