25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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2.6.2. Test Procedure—Design Example with the IEEE 1588v2 Feature

Follow these steps to test the design examples in hardware using PMA serial loopback:

Note: The design example starts with default data rate of 25G.
  1. Perform data rate switching to 10G:
    1. In Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources & Probes Editor tool to open the default source and probe GUI.
    2. Set the source bit[1] in source and probe to 1.
    3. In the System Console panel, type the following commands as below to set the correct clock period for the required TX and RX MAC clock frequency in 10G speed mode:
      reg_write 0xA05 0x66666
      reg_write 0xB05 0x66666
  2. Perform data rate switching to 25G:
    1. In Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources & Probes Editor tool to open the default source and probe GUI.
    2. Set the source bit[1] in source and probe to 0.
    3. In the System Console panel, type the following commands as below to set the correct clock period for the required TX and RX MAC clock frequency in 25G speed mode:
      reg_write 0xA05 0x28F5C
      reg_write 0xB05 0x28F5C
    Note: 0xA05 is register that configure TX_PTP_CLK_PERIOD. 0xB05 is register that configure RX_PTP_CLK_PERIOD.
  3. Perform system reset release after executing the data rate reconfiguration:
    1. Click Tools > In-System Sources & Probes Editor tool for the default Source and Probe GUI.
    2. Toggle the system reset signal (Source[0]) from 0 to 1 to apply the reset and return the system reset signal back to 0 to release the system from the reset state.
    3. Monitor the Probe signals and ensure that the status is valid.
  4. To perform internal serial loopback test, refer to the Test Procedure—Design Example Without the IEEE 1588v2 Feature section of this chapter.

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