25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

Download
ID 683252
Date 6/18/2020
Public
Document Table of Contents

3.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature

The simulation test case performs the following actions:

  1. Instantiates and ATX PLL.
  2. Waits for RX clock and PHY status signal to settle.
  3. Prints PHY status.
  4. Analyzes the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."
Figure 18. Sample Simulation Output for Design Example Without the IEEE 1588v2 Feature

Did you find the information on this page useful?

Characters remaining:

Feedback Message