25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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5.2. Design Example Registers

Table 15.  Hardware Design Example Register Map for 25G Ethernet Intel® FPGA IP Core for Intel® Stratix® 10 DevicesYou access these registers with the reg_read and reg_write functions in the System Console.

Word Offset

Register Category

Variant: Single-Channel
0X0000–0X0DFF Register range to access the Status Registers.
0X4000–0X7FFF Register range to access the Reconfiguration Registers.
0X10000–0X10001 Register range to access the Reconfiguration Registers module for 10G/25G switching.
0x1020 32-bit average_offset_fnsec_r register:
  • Read this register to obtain average offset value [47:16] in fractional nanosecond, which is derived from the offset adjustment data [96:0] of the PTP slave.
0x1021 32-bit average_offset_fnsec_to_mem register:
  • Read this register to obtain average offset value [15:0] in fractional nanosecond, which is derived from the offset adjustment data [96:0] of the PTP slave.
  • Bit [31:16]: Reserved.
0x1030 32-bit average_delay_fnsec_r register:
  • Read this register to obtain average delay value [47:16] in fractional nanosecond, which is derived from the offset adjustment data [191:96] of the PTP slave.
0x1031 32-bit average_delay_fnsec_to_mem register:
  • Read this register to obtain average delay value [15:0] in fractional nanosecond, which is derived from the offset adjustment data [191:96] of the PTP slave.
  • Bit [31:16]: Reserved.
Variant: Multi-Channel
0x00000–0x30DFF For multi-channel design examples, the base address of all channels are incremented with 0x10000. This corresponds to:
  • Channel 0 Range: 0x00300–00DFF
  • Channel 1 Range: 0x10300–10DFF
  • Channel 2 Range: 0x20300–20DFF
  • Channel 3 Range: 0x30300–30DFF
0x04000-0x37FFF For multi-channel design examples, the base address of all channels are incremented with 0x10000. This corresponds to:
  • Channel 0 Range: 0x04000-0x07FFF
  • Channel 1 Range: 0x14000-0x17FFF
  • Channel 2 Range: 0x24000-0x27FFF
  • Channel 3 Range: 0x34000-0x37FFF
Note:
  1. For Intel® Stratix® 10 H-tile production device, disable the background calibration prior to accessing the transceiver core reconfiguration register, as described in the Disabling Background Calibration section of the 25G Ethernet Intel® FPGA IP User Guide.
  2. Dynamic reconfiguration switching for 10G/25G is not available for multi-channel designs.
  3. For single-channel design example, 0x4000 is the base address of the PHY registers. For example, to read the background calibration register, type reg_read 0x4542.
  4. For multi-channel design example, the base address of the PHY registers is 0x4000 + (0x10000 * <link num>). For example, to read the background calibration register at channel 2, type reg_read 0x24542.

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