25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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2.3. Functional Description

The 10G/25G Ethernet single-channel design example consists of two core variants—MAC+PCS+PMA and MAC+PCS. The following block diagrams show the design components and the top-level signals of the two core variants in the 10G/25G Ethernet single-channel design example.

Figure 6. Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) Without the IEEE 1588v2 Feature
Figure 7. Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) with the IEEE 1588v2 Feature
Figure 8. Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) Without the IEEE 1588v2 Feature
Figure 9. Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) with the IEEE 1588v2 Feature

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