25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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4.6.1. Test Procedure

Follow these steps to test the design example in hardware:

  1. Before you run the hardware testing for this design example, you must reset the system:
    1. Click Tools > In-System Sources & Probes Editor tool for the default Source and Probe GUI.
    2. Toggle the system reset signal (Source[0]) from 0 to 1 to apply the reset and return the system reset signal back to 0 to release the system from the reset state.
    3. Monitor the Probe signals and ensure that the status is valid.
  2. To perform internal serial loopback test, refer to the Test Procedure—Design Example Without the IEEE 1588v2 Feature section of the 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices chapter.
    Note: link_num is valid for 0 to 3 only.

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