25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
Document Table of Contents

3.1. Features

  • Supports single Ethernet channel operating at 25G.
  • Generates design example with IEEE 1588v2 feature.
  • Generates design example with RS-FEC feature.
  • Generates design example separately from Intel® Stratix® 10 Transceiver Native PHY.
  • Provides testbench and simulation script.

Did you find the information on this page useful?

Characters remaining:

Feedback Message