25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
Document Table of Contents

1.2.1. Design Example Parameters

Table 2.  Parameters in the Example Design Tab
Parameter Description
Example Design Available example designs for the IP parameter settings.
Example Design Files

The files to generate for the different development phase.

  • Simulation—generates the necessary files for simulating the example design.
  • Synthesis—generates the synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Edition software for hardware testing and perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog.
Select Board Supported hardware for design implementation. When you select an Intel FPGA development board, use device 1SX280LU2F50E1VG as the Target Device for design example generation.

If this menu is not available, there is no supported board for the options that you select.

Stratix® 10 GX Signal Integrity L-Tile (Prod) Development Kit: This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device of 1SX280LU2F50E1VG. If your board revision has a different device grade, you can change the target device.

None: This option excludes the hardware aspects for the design example.

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