25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683252
Date 6/18/2020
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4.3.1. Design Components

Table 11.  Design Components
Component Description
25G Ethernet Intel® FPGA IP

Consists of MAC, PCS, and Transceiver PHY, with the following configuration:

  • Core Variant: MAC+PCS+PMA
  • Enable RS-FEC: Not selected
  • Enable flow control: Optional
  • Enable link fault generation: Optional
  • Enable preamble passthrough: Optional
  • Enable statistics collection: Optional
  • Enable MAC statistics counters: Optional
  • Enable IEEE 1588: Not selected
  • Enable 10G/25G dynamic rate switching: Not selected
  • Enable Native PHY Debug Master Endpoint (NPDME): Optional
  • Reference clock frequency: 644.531250/322.265625
ATX PLL Generates TX serial clocks for the 25G transceiver.
Client logic Consists of:
  • Traffic generator, which generates burst packets to the 25G Ethernet Intel® FPGA IP core for transmission.
  • Traffic monitor, which receives burst packets from the 25G Ethernet Intel® FPGA IP core.
Source and Probe Source and probe signals, including system reset input signal, which you can use for debugging.

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