25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683252
Date 6/18/2020
Public
Document Table of Contents

4.3. Functional Description

The 25G Ethernet multi-channel design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

Figure 21. Block Diagram—25G Ethernet Multi-Channel Design Example (MAC+PCS+PMA Core Variant)

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