Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

2. Intel® MAX® 10 External Memory Interface Architecture and Features

The external memory interface architecture of Intel® MAX® 10 devices is a combination of soft and hard IPs.
Figure 1. High Level Overview of Intel® MAX® 10 External Memory Interface SystemThis figure shows a high level overview of the main building blocks of the external memory interface system in Intel® MAX® 10 devices.


  • The full rate data capture and write registers use the DDIO registers inside the I/O elements.
  • PHY logic is implemented as soft logic in the core fabric.
  • The memory controller is the intermediary between the user logic and the rest of the external memory interface system. The memory controller IP is a soft memory controller that operates at half rate. You can also use your own soft memory controller or a soft memory controller IP from Intel's third-party FPGA partners.
  • The physical layer (PHY) serves as the bridge between the memory controller and the external memory DRAM device.

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