Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

5.1.1. UniPHY Parameters—PHY Settings

There are three groups of options: General Settings, Clocks, and Advanced PHY Settings.
Table 10.  PHY Settings - General Settings
Parameter Description
Speed Grade
Specifies the speed grade of the targeted FPGA device that affects the generated timing constraints and timing reporting.
Note: For Intel® MAX® 10 devices, DDR3 and LPDDR2 is supported only for speed grade –6, and DDR2 for speed grades –6 and –7.
Generate PHY only

Turn on this option to generate the UniPHY IP without a memory controller.

When you turn on this option, the AFI interface is exported so that you can easily connect your own memory controller.

Table 11.  PHY Settings - Clocks
Parameter Description
Memory clock frequency

The frequency of the clock that drives the memory device. Use up to 4 decimal places of precision.

To obtain the maximum supported frequency for your target memory configuration, refer to the External Memory Spec Estimator page on www.intel.com.

Achieved memory clock frequency

The actual frequency the PLL generates to drive the external memory interface (memory clock).

PLL reference clock frequency

The frequency of the input clock that feeds the PLL. Use up to 4 decimal places of precision.

Rate on Avalon-MM interface

The width of data bus on the Avalon® memory-mapped interface.

The Intel® MAX® 10 supports only Half rate, which results in a width of 4× the memory data width.

Achieved local clock frequency

The actual frequency the PLL generates to drive the local interface for the memory controller (AFI clock).

Table 12.  DDR3 SDRAM PHY Settings - Advanced PHY Settings
Parameter Description
Supply voltage

The supply voltage and sub-family type of memory.

This option is available for DDR3 SDRAM only.

I/O standard

The I/O standard voltage.

Set the I/O standard according to your design’s memory standard.

Reconfigurable PLL location

If you set the PLL used in the UniPHY IP memory interface to be reconfigurable at run time, you must specify the location of the PLL.

This assignment generates a PLL that can only be placed in the given sides.

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