Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

2.7. Intel® MAX® 10 Address/Command Path

Intel's soft memory controller IP and PHY IP operate at half rate and issue address/command instructions at half-rate.
  • You must send the address/command instructions to the external DRAM center-aligned with respect to the external memory clock (CK/CK#).
  • For LPDDR2 applications, the address/command path is double data rate (DDR). Dedicated DDIO output registers in the I/O periphery clocks out the address/command instructions to the external DRAM.
  • For DDR2/3 applications, the address/command path is single data rate (SDR). Instead of dedicated DDIO output registers, simple output I/O registers in the I/O periphery clocks out the address/command instructions to the external DRAM device.

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