Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

2.8. Intel® MAX® 10 PHY Clock (PHYCLK) Network

The PHYCLK network is a dedicated high-speed and low skew balanced clock tree that provides better clock skew for external memory interface applications.

In Intel® MAX® 10 devices, only the top right PLL is routed to the PHYCLK tree. Therefore, the PHYCLK tree is available only for the I/O banks on the right side of the Intel® MAX® 10 10M16, 10M25, 10M40, and 10M50 devices.

Figure 7. I/O Banks for External Memory Interfaces This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


Did you find the information on this page useful?

Characters remaining:

Feedback Message