Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

5.1.3. UniPHY Parameters—Memory Timing

Use the Memory Timing options to apply the memory timings from your memory manufacturer’s data sheet.
Table 17.  Memory TimingFor each parameter, refer to the memory vendor data sheet.
Parameter Applies To Description Set According To
tIS (base) DDR2, DDR3, LPDDR2

Address and control setup to CK clock rise.

Memory speed grade
tIH (base) DDR2, DDR3, LPDDR2

Address and control hold after CK clock rise.

Memory speed grade
tDS (base) DDR2, DDR3, LPDDR2

Data setup to clock (DQS) rise.

Memory speed grade
tDH (base) DDR2, DDR3, LPDDR2

Data hold after clock (DQS) rise.

Memory speed grade
tDQSQ DDR2, DDR3, LPDDR2

DQS, DQS# to DQ skew, per access.

Memory speed grade
tQHS DDR2, LPDDR2

DQ output hold time from DQS, DQS# (absolute time value).

Memory speed grade
tQH DDR3

DQ output hold time from DQS, DQS# (percentage of tCK).

Memory speed grade
tDQSCK DDR2, DDR3

DQS output access time from CK/CK#.

Memory speed grade
tDQSCK (max) LPDDR2
tDQSCK Delta Short LPDDR2

Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160 ns rolling window.

Memory speed grade
tDQSCK Delta Medium LPDDR2

Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 1.6 µs rolling window.

Memory speed grade
tDQSCK Delta Long LPDDR2

Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 32ms rolling window.

Memory speed grade
tDQSS DDR2, DDR3, LPDDR2

First latching edge of DQS to associated clock edge (percentage of tCK).

Memory speed grade
tDQSH DDR2, LPDDR2

DQS Differential High Pulse Width (percentage of tCK). Specifies the minimum high time of the DQS signal received by the memory.

Memory speed grade
tQSH DDR3
tDSH DDR2, DDR3, LPDDR2

DQS falling edge hold time from CK (percentage of tCK).

Memory speed grade
tDSS DDR2, DDR3, LPDDR2

DQS falling edge to CK setup time (percentage of tCK).

Memory speed grade
tINIT DDR2, DDR3, LPDDR2

Memory initialization time at power-up.

Memory speed grade
tMRD DDR2, DDR3

Load mode register command period.

Memory speed grade
tMRW LPDDR2
tRAS DDR2, DDR3, LPDDR2

Active to precharge time.

Memory speed grade
tRCD DDR2, DDR3, LPDDR2

Active to read or write time.

Memory speed grade
tRP DDR2, DDR3, LPDDR2

Precharge command period.

Memory speed grade
tREFI DDR2, DDR3

Refresh command interval.

Memory speed grade and temperature range
tREFIab LPDDR2

Refresh command interval (all banks).

Memory speed grade
tRFC DDR2, DDR3

Auto-refresh command interval.

Memory device capacity
tRFCab LPDDR2

Auto-refresh command interval (all banks).

Memory device capacity
tWR DDR2, DDR3, LPDDR2

Write recovery time.

Memory speed grade
tWTR DDR2, DDR3, LPDDR2

Write to read period.

Calculate the value based on the memory clock frequency.

Memory speed grade and memory clock frequency
tFAW DDR2, DDR3, LPDDR2

Four active window time.

Memory speed grade and page size
tRRD DDR2, DDR3, LPDDR2

RAS to RAS delay time.

Calculate the value based on the memory clock frequency.

Memory speed grade, page size and memory clock frequency
tRTP DDR2, DDR3, LPDDR2

Read to precharge time.

Calculate the value based on the memory clock frequency.

Memory speed grade and memory clock frequency

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