Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

2.5.1. DDR Input Registers

The DDR input capture registers in Intel® MAX® 10 devices are implemented in the I/O periphery.
Figure 3. External Memory Interface Read Datapath


Figure 4. External Memory Interface Read Datapath Timing


In Intel® MAX® 10 external memory interfaces, post-amble is not a concern because the read data strobe signal, DQS, is not used during read operation.

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