Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

3.3. Guidelines: Intel® MAX® 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation

While implementing certain external memory interface standards, the number of I/O pins available is limited.
  • While implementing DDR2—for 25 percent of the remaining I/O pins available in I/O banks 5 and 6, you can assign them only as input pins.
  • While implementing DDR3 or LPDDR2—the I/O pins listed in the following table are not available for use. Of the remaining I/O pins, you can assign only 75 percent of the available I/O pins in I/O banks 5 and 6 for normal I/O operation.
Table 9.  Unavailable I/O Pins While Implementing DDR3 or LPDDR2 External Memory Interfaces in Certain Device Packages—Preliminary
Device Package
F256 U324 F484 F672

10M16

N16

P16

R15

P15

R18

P18

E16

D16

U21

U22

M21

L22

F21

F20

E19

F18

10M25

N16

P16

U21

U22

M21

L22

F21

F20

E19

F18

F17

E17

10M40

10M50

N16

P16

U21

U22

M21

L22

F21

F20

E19

F18

F17

E17

W23

W24

U25

U24

T24

R25

R24

P25

K23

K24

J23

H23

G23

F23

G21

G22

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