Intel® MAX® 10 External Memory Interface User Guide

Download PDF
ID 683087
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 External Memory Interface Overview 2. Intel® MAX® 10 External Memory Interface Architecture and Features 3. Intel® MAX® 10 External Memory Interface Design Considerations 4. Intel® MAX® 10 External Memory Interface Implementation Guides 5. UniPHY IP References for Intel® MAX® 10 Devices 6. Intel® MAX® 10 External Memory Interface User Guide Archives 7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide
1. Intel® MAX® 10 External Memory Interface Overview x
1.1. Intel® MAX® 10 External Memory Interface Support and Performance
2. Intel® MAX® 10 External Memory Interface Architecture and Features x
2.1. Intel® MAX® 10 I/O Banks for External Memory Interface 2.2. Intel® MAX® 10 DQ/DQS Groups 2.3. Intel® MAX® 10 External Memory Interfaces Maximum Width 2.4. Intel® MAX® 10 Memory Controller 2.5. Intel® MAX® 10 External Memory Read Datapath 2.6. Intel® MAX® 10 External Memory Write Datapath 2.7. Intel® MAX® 10 Address/Command Path 2.8. Intel® MAX® 10 PHY Clock (PHYCLK) Network 2.9. Phase Detector for VT Tracking 2.10. On-Chip Termination 2.11. Phase-Locked Loop 2.12. Intel® MAX® 10 Low Power Feature
2.5. Intel® MAX® 10 External Memory Read Datapath x
2.5.1. DDR Input Registers
2.6. Intel® MAX® 10 External Memory Write Datapath x
2.6.1. DDR Output Registers
3. Intel® MAX® 10 External Memory Interface Design Considerations x
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations 3.2. LPDDR2 Design Considerations 3.3. Guidelines: Intel® MAX® 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation 3.4. Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 3.5. Guidelines: Reading the Intel® MAX® 10 Pin-Out Files
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations x
3.1.1. DDR2/DDR3 External Memory Interface Pins 3.1.2. DDR2/DDR3 Recommended Termination Schemes for Intel® MAX® 10 Devices
3.1.1. DDR2/DDR3 External Memory Interface Pins x
3.1.1.1. Intel® MAX® 10 Data and Data Clock (Data Strobe) Pins 3.1.1.2. Data Mask Pins 3.1.1.3. DDR2/DDR3 Error Correction Coding Pins 3.1.1.4. DDR2/DDR3 Address and Control/Command Pins 3.1.1.5. Memory Clock Pins
3.1.1.1. Intel® MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.1.1.1.1. Intel® MAX® 10 I/O Bank DQ/DQS Support for DDR2/DDR3
3.2. LPDDR2 Design Considerations x
3.2.1. LPDDR2 External Memory Interface Pins 3.2.2. LPPDDR2 Power Supply Variation Constraint 3.2.3. LPDDR2 Recommended Termination Schemes for Intel® MAX® 10 Devices
3.2.1. LPDDR2 External Memory Interface Pins x
3.2.1.1. Intel® MAX® 10 Data and Data Clock (Data Strobe) Pins 3.2.1.2. Data Mask Pins 3.2.1.3. LPDDR2 Address and Control/Command Pins 3.2.1.4. Memory Clock Pins
3.2.1.1. Intel® MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.2.1.1.1. Intel® MAX® 10 I/O Bank DQ/DQS Support for LPDDR2
4. Intel® MAX® 10 External Memory Interface Implementation Guides x
4.1. UniPHY IP Core 4.2. LPDDR2 External Memory Interface Implementation 4.3. DDR2 and DDR3 External Memory Interface Implementation
4.2. LPDDR2 External Memory Interface Implementation x
4.2.1. Supported LPDDR2 Topology
4.3. DDR2 and DDR3 External Memory Interface Implementation x
4.3.1. Intel® MAX® 10 Supported DDR2 or DDR3 Topology
5. UniPHY IP References for Intel® MAX® 10 Devices x
5.1. UniPHY Parameter Settings for Intel® MAX® 10
5.1. UniPHY Parameter Settings for Intel® MAX® 10 x
5.1.1. UniPHY Parameters—PHY Settings 5.1.2. UniPHY Parameters—Memory Parameters 5.1.3. UniPHY Parameters—Memory Timing 5.1.4. UniPHY Parameters—Board Settings 5.1.5. UniPHY Parameters—Controller Settings 5.1.6. UniPHY Parameters—Diagnostics
1. Intel® MAX® 10 External Memory Interface Overview
2. Intel® MAX® 10 External Memory Interface Architecture and Features
3. Intel® MAX® 10 External Memory Interface Design Considerations
4. Intel® MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for Intel® MAX® 10 Devices
6. Intel® MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide

2.4. Intel® MAX® 10 Memory Controller

Intel® MAX® 10 devices use the HPC II external memory controller.
Table 4.  Features of the Intel® MAX® 10 Memory Controller
Feature Description
Half-Rate Operation

The controller and user logic can run at half the memory clock rate.

Controller Latency

The controller has a low best-case time between a read request or a write request on the local interface, and the memory command being sent to the AFI interface.

Data Reordering

The memory controller reorders read and write requests as necessary to achieve the most efficient throughput of data.

Starvation Control

The controller implements a starvation counter to limit the length of time that a command can go unserved. This counter ensures that lower-priority requests are not overlooked indefinitely due to data reordering. You can set a starvation limit, to ensure that a waiting command is served immediately, when the starvation counter reaches the specified limit.

Priority Bypass

The memory controller accepts user requests to bypass the priority established by data reordering. When the controller detects a high-priority request, it allows that request to bypass the current queue. The high-priority request is then processed immediate, reducing latency.

Standard Interface

The memory controller uses Avalon® streaming interface as its native interface, allowing the flexibility to extend to Avalon® memory-mapped interface, AXI, or a proprietary protocol with an adapter.

Avalon® Memory-Mapped Interface Data Slave Local Interface

The controller supports the Intel Avalon® memory-mapped interface protocol.

Bank Management

The memory controller intelligently keeps a page open based on incoming traffic, improving efficiency, especially for random traffic.

Streaming Reads and Writes

The memory controller has the ability to issue reads or writes continuously to sequential addresses each clock cycle, if the bank is open. This feature allows for the passage of large amounts of data, with high efficiency.

Bank Interleaving

The memory controller has the ability to issue reads or writes continuously to random addresses. The bank addresses must be correctly cycled by user logic.

Predictive Bank Management

The memory controller has the ability to issue bank management commands early, so that the correct row is already open when a read or write request occurs. This feature allows for increased efficiency.

Quasi-1T Address/Command Half-Rate

One controller clock cycle equals two memory clock cycles in a half-rate interface. To maximize command bandwidth, the memory controller provides the option to allow two memory commands on every controller clock cycle. The controller is constrained to issue a row command on the first clock phase and a column command on the second clock phase, or vice versa. Row commands include activate and precharge commands; column commands include read and write commands.

Built-In Burst Adaptor

The memory controller has the ability to accept bursts of arbitrary size on the local interface, and map these to efficient memory commands.

Self-Refresh Controls and User Auto-Refresh Controls

The memory controller has the ability to issue self-refresh commands and allow user auto-refresh through a sideband interface.

Enable Auto Power-Down

The memory controller has the ability to power-down if no commands are received.

Level Two Title