2.4. Intel® MAX® 10 Memory Controller
The controller and user logic can run at half the memory clock rate.
The controller has a low best-case time between a read request or a write request on the local interface, and the memory command being sent to the AFI interface.
The memory controller reorders read and write requests as necessary to achieve the most efficient throughput of data.
The controller implements a starvation counter to limit the length of time that a command can go unserved. This counter ensures that lower-priority requests are not overlooked indefinitely due to data reordering. You can set a starvation limit, to ensure that a waiting command is served immediately, when the starvation counter reaches the specified limit.
The memory controller accepts user requests to bypass the priority established by data reordering. When the controller detects a high-priority request, it allows that request to bypass the current queue. The high-priority request is then processed immediate, reducing latency.
The memory controller uses Avalon® streaming interface as its native interface, allowing the flexibility to extend to Avalon® memory-mapped interface, AXI, or a proprietary protocol with an adapter.
|Avalon® Memory-Mapped Interface Data Slave Local Interface
The controller supports the Intel Avalon® memory-mapped interface protocol.
The memory controller intelligently keeps a page open based on incoming traffic, improving efficiency, especially for random traffic.
|Streaming Reads and Writes
The memory controller has the ability to issue reads or writes continuously to sequential addresses each clock cycle, if the bank is open. This feature allows for the passage of large amounts of data, with high efficiency.
The memory controller has the ability to issue reads or writes continuously to random addresses. The bank addresses must be correctly cycled by user logic.
|Predictive Bank Management
The memory controller has the ability to issue bank management commands early, so that the correct row is already open when a read or write request occurs. This feature allows for increased efficiency.
|Quasi-1T Address/Command Half-Rate
One controller clock cycle equals two memory clock cycles in a half-rate interface. To maximize command bandwidth, the memory controller provides the option to allow two memory commands on every controller clock cycle. The controller is constrained to issue a row command on the first clock phase and a column command on the second clock phase, or vice versa. Row commands include activate and precharge commands; column commands include read and write commands.
|Built-In Burst Adaptor
The memory controller has the ability to accept bursts of arbitrary size on the local interface, and map these to efficient memory commands.
|Self-Refresh Controls and User Auto-Refresh Controls
The memory controller has the ability to issue self-refresh commands and allow user auto-refresh through a sideband interface.
|Enable Auto Power-Down
The memory controller has the ability to power-down if no commands are received.