3.1.2. DDR2/DDR3 Recommended Termination Schemes for Intel® MAX® 10 Devices
If you are creating interfaces with multiple DDR2 or DDR3 components where the address, command, and memory clock pins are connected to more than one load, follow these steps:
- Simulate the system to get the new slew rate for the DQ/DQS, DM, address and command, and clock signals.
- Use the derated tIS and tIH specifications from the DDR2 or DDR3 datasheet based on the simulation results.
- If timing deration causes your interface to fail timing requirements, consider duplication of these signals to lower their loading, and hence improve timing.
|Signal Type||SSTL 18 I/O Standard||FPGA–End Discrete Termination||Memory–End Termination 1||Memory I/O Standard|
|DQ/DQS||Class I Rs = 50 Ω||50 Ω parallel to VTT discrete||ODT75 4||HALF 5|
|DM||Class I Rs = 50 Ω||—||ODT754||HALF5|
|Address and command||Class I with maximum drive strength||—||56 Ω parallel to VTT discrete||—|
|Clock||Differential Class I Rs = 50 Ω||—||—|
|I/O Standard||RS OCT||On Board Termination|
|SSTL 15 Class 1||50 Ω without calibration||80 Ω resistor||40 Ω resistor|
|Memory Interface Standard||I/O Standard||RS OCT||RUP, RDN (Ω)|
Did you find the information on this page useful?