Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Document Table of Contents

3.1.2. DDR2/DDR3 Recommended Termination Schemes for Intel® MAX® 10 Devices

If you are creating interfaces with multiple DDR2 or DDR3 components where the address, command, and memory clock pins are connected to more than one load, follow these steps:

  1. Simulate the system to get the new slew rate for the DQ/DQS, DM, address and command, and clock signals.
  2. Use the derated tIS and tIH specifications from the DDR2 or DDR3 datasheet based on the simulation results.
  3. If timing deration causes your interface to fail timing requirements, consider duplication of these signals to lower their loading, and hence improve timing.
Note: Class I and Class II termination schemes in the following tables refer to drive strength and not physical termination.
Table 5.  Termination Recommendations for Intel® MAX® 10 DDR2 Component
Signal Type SSTL 18 I/O Standard FPGA–End Discrete Termination Memory–End Termination 1 Memory I/O Standard
DQ/DQS Class I Rs = 50 Ω 50 Ω parallel to VTT discrete ODT75 4 HALF 5
DM Class I Rs = 50 Ω ODT754 HALF5
Address and command Class I with maximum drive strength 56 Ω parallel to VTT discrete
Clock Differential Class I Rs = 50 Ω
  • x1 = 100 Ω differential6
  • x2 = 200 Ω differential7
Table 6.  On Board Termination Recommendation for Intel® MAX® 10 DDR3 ComponentFor Intel® MAX® 10 devices, on board termination is required for DDR3 component.
I/O Standard RS OCT On Board Termination
FPGA–End Memory-End
SSTL 15 Class 1 50 Ω without calibration 80 Ω resistor 40 Ω resistor
Table 7.  Supported External Memory Interface Termination Scheme for DDR3 and DDR2
Memory Interface Standard I/O Standard RS OCT RUP, RDN (Ω)
DDR3 SSTL-15 25 25
34 34
40 40
50 50
DDR3L SSTL-135 34 34
40 40
DDR2 SSTL-18 25 25
50 50
4 ODT75 vs. ODT50 on the memory has the effect of opening the eye more, with a limited increase in overshoot/undershoot.
5 HALF is reduced drive strength.
6 x1 is a single-device load.
7 x2 is a two-device load.

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