Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.10.31 21.1
  • Updated the Memory Standards Supported by the Soft Memory Controller for Intel® MAX® 10 Devices table.
    • Removed contact information for –A6 speed grade devices.
    • Added note on automotive-grade devices do not support external memory interfaces.
2021.11.01 21.1 Removed –I6 speed grade from contact information in the Memory Standards Supported by the Soft Memory Controller for Intel® MAX® 10 Devices table. All OPNs for –I6 speed grade are available in the Intel® Quartus® Prime Standard Edition software version 21.1 onwards.
2021.04.01 16.1
  • Updated Table Termination Recommendations for Intel MAX 10 DDR2 Component:
    • Changed SSTL 18 I/O Standard for DQ/DQS, DM and Clock Signal Type.
    • Added FGPA - End Discrete Termination for Address and Command Signal Type.
    • Changed Memory-End Termination 1 for DM Signal Type.
    • Added Memory I/O Standard for DM Signal Type.
2020.10.15 16.1
  • Renamed the document as Intel® MAX® 10 External Memory Interface User Guide.
  • Updated Intel® MAX® 10 I/O Banks for External Memory Interface.
  • Updated for latest Intel branding standards.
Date Version Changes
February 2017 2017.02.21
  • Rebranded as Intel.
October 2016 2016.10.28
  • Updated Memory Standards Supported by the Soft Memory Controller for MAX 10 devices table.
May 2016 2016.05.02
  • Updated UniPHY IP core parameter settings for LPDDR2, DDR2 and DDR3.
  • Updated Supported Maximum External Memory Interface Width in Intel® MAX® 10 Device Packages table.
  • Added Intel® MAX® 10 External Memory Interface User Guide Archives table.
  • Updated DDR2, DDR3 and LPDDR2 can use only user I/O pins from banks 5 and 6 of Intel® MAX® 10 devices to generate address and control or command signals..
November 2015 2015.11.02
  • Added links to Intel® MAX® 10 DDR3 UniPHY IP core reference design.
  • Added topic that lists the maximum external memory interface widths supported for different Intel® MAX® 10 device packages.
  • Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added a link to Introduction to Altera IP Cores.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.11 Added on board termination recommendation for DDR3 component.
May 2015 2015.05.04
  • Updated the footnote in the topic about external memoy interface support and performance to specify that the default maximum frequency for LPDDR2 is 167 MHz.
  • Removed the F672 package from the 10M25 device.
  • Removed the note about contacting Altera for DDR3, DDR3L, DDR2, and LPDDR2 external memory interface support. The Intel® Quartus® Prime software supports these external memory interfaces from version 15.0.
  • Added a topic about the PHYCLK network.
  • Moved information about recommended LPDDR2 termination scheme into a new topic under LPDDR2 design considerations section. The information was previously in the topic about recommended DDR2/DDR3 termination schemes.
  • Updated the guidelines about board design requirement to improve clarity.
  • Updated and added related information links to relevant information.
  • Added a topic about the low power feature available from version 15.0 of the Intel® Quartus® Prime software.
  • Updated the topic about the phase detector to add a figure showing the VT tracking system overview.
December 2014 2014.12.15
  • Changed Altera MAX 10 EMIF IP core to UniPHY IP core.
  • Removed reference to DIMM in a footnote under the table that lists the termination recommendations for DDR2 component. The UniPHY IP core for Intel® MAX® 10 does not support DIMM.
  • Added a list of the MAX 10 memory controller features.
  • Added "Preliminary" tag to the table that lists the I/Os unavailable in certain MAX 10 packages while implementing DDR3 or LPDDR2 external memory interfaces.
  • Updated the board design requirement with additional guidelines.
  • Added information for the MAX 10 external memory interface UniPHY IP core. This addition includes the chapters about external memory interface implementation and IP core references.
  • Edited texts and added related information links to improve clarity.
September 2014 2014.09.22 Initial release.

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