Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

5.1.5. UniPHY Parameters—Controller Settings

There are four groups of options: Avalon® Interface, Low Power Mode, Efficiency, and Configuration, Status and Error Handling.
Table 21.  Controller Settings - Avalon® Interface
Parameter Descriptions
Generate power-of-2 data bus widths for Qsys or SOPC Builder

Rounds down the Avalon® memory-mapped interface side data bus to the nearest power of 2. You must enable this option for Platform Designer (Qsys) systems.

If this option is enabled, the Avalon® data buses are truncated to 256 bits wide. One Avalon® read-write transaction of 256 bit width maps to four memory beat transactions, each of 72 bits (8 MSB bits are zero, while 64 LSB bits carry useful content). The four memory beats may comprise an entire burst length-of-4 transaction, or part of a burst-length-of-8 transaction.

Generate SOPC Builder compatible resets

This option is not required when using the parameter editor or Platform Designer.

Maximum Avalon-MM burst length

Specifies the maximum burst length on the Avalon® memory-mapped interface bus. Affects the AVL_SIZE_WIDTH parameter.

Enable Avalon-MM byte-enable signal

When you turn on this option, the controller adds the byte enable signal (avl_be) for the Avalon® memory-mapped interface bus to control the data mask (mem_dm) pins going to the memory interface. You must also turn on Enable DM pins if you are turning on this option.

When you turn off this option, the byte enable signal (avl_be) is not enabled for the Avalon® memory-mapped interface bus, and by default all bytes are enabled. However, if you turn on Enable DM pins with this option turned off, all write words are written.

Avalon® interface address width

The address width on the Avalon® memory-mapped interface.

Avalon® interface data width

The data width on the Avalon® memory-mapped interface.

Table 22.  Controller Settings - Low Power Mode
Parameter Description
Enable Self-Refresh Controls

Enables the self-refresh signals on the controller top-level design. These controls allow you to control when the memory is placed into self-refresh mode.

Enable Deep Power-Down Controls

Enables the Deep-Powerdown signals on the controller top level. These controls allow you to control when the memory is placed in Deep-Powerdown mode.

This option is available only for LPDDR2 SDRAM.

Enable Auto Power-Down

Allows the controller to automatically place the memory into power-down mode after a specified number of idle cycles. Specifies the number of idle cycles after which the controller powers down the memory in the auto-power down cycles parameter.

Auto Power-Down Cycles

The number of idle controller clock cycles after which the controller automatically powers down the memory. The legal range is from 1 to 65,535 controller clock cycles.

Table 23.  Controller Settings - Efficiency
Parameter Description
Enable User Auto-Refresh Controls

Enables the user auto-refresh control signals on the controller top level. These controller signals allow you to control when the controller issues memory autorefresh commands.

Enable Auto-Precharge Control

Enables the autoprecharge control on the controller top level. Asserting the autoprecharge control signal while requesting a read or write burst allows you to specify whether the controller should close (autoprecharge) the currently open page at the end of the read or write burst.

Local-to-Memory Address Mapping

Allows you to control the mapping between the address bits on the Avalon® memory-mapped interface and the chip, row, bank, and column bits on the memory:

  • Chip-Row-Bank-Col—improves efficiency with sequential traffic.
  • Chip-Bank-Row-Col—improves efficiency with random traffic.
  • Row-Chip-Bank-Col—improves efficiency with multiple chip select and sequential traffic.
Command Queue Look-Ahead Depth

Selects a look-ahead depth value to control how many read or writes requests the look-ahead bank management logic examines. Larger numbers are likely to increase the efficiency of the bank management, but at the cost of higher resource usage. Smaller values may be less efficient, but also use fewer resources. The valid range is from 1 to 16.

Enable Reordering

Allows the controller to perform command and data reordering that reduces bus turnaround time and row/bank switching time to improve controller efficiency.

Starvation limit for each command

Specifies the number of commands that can be served before a waiting command is served. The valid range is from 1 to 63.

Table 24.  Controller Settings - Configuration, Status and Error Handling
Parameter Description
Enable Configuration and Status Register Interface

Enables run-time configuration and status interface for the memory controller. This option adds an additional Avalon® memory-mapped interface slave port to the memory controller top level, which you can use to change or read out the memory timing parameters, memory address sizes, mode register settings and controller status. If Error Detection and Correction Logic is enabled, the same slave port also allows you to control and retrieve the status of this logic.

CSR port host interface

Specifies the type of connection to the CSR port. The port can be exported, internally connected to a JTAG Avalon® Master, or both:

  • Internal (JTAG)—connects the CSR port to a JTAG Avalon® Master.
  • Avalon® -MM Slave—exports the CSR port.
  • Shared—exports and connects the CSR port to a JTAG Avalon® Master.
Enable Error Detection and Correction Logic

Enables ECC for single-bit error correction and double-bit error detection. Intel® MAX® 10 devices supports ECC only for 16 bits + 8 bits ECC memory configuration.

Enable Auto Error Correction

Allows the controller to perform auto correction when a single-bit error is detected by the ECC logic.

To turn this on, you must first turn on Enable Error Detection and Correction Logic.

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