Intel® MAX® 10 External Memory Interface User Guide

ID 683087
Date 10/31/2022
Public
Document Table of Contents

2.11. Phase-Locked Loop

For the external memory interface, the PLL generates the memory clock, write clock, capture clock, and the logic–core clock.
  • The memory clock provides clock for DQS write strobe, and address and command signals.
  • The write clock that is shifted –90° from the memory clock provides clock for DQ signals during memory writes.

You can use the PLL reconfiguration feature to calibrate the read–capture phase shift to balance the setup and hold margins. At startup, the sequencer calibrates the capture clock.

For external memory interfaces in Intel® MAX® 10 devices, you must use the top right PLL (PLL 2).

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