1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide
2.1. MAX® 10 I/O Banks for External Memory Interface
2.2. MAX® 10 DQ/DQS Groups
2.3. MAX® 10 External Memory Interfaces Maximum Width
2.4. MAX® 10 Memory Controller
2.5. MAX® 10 External Memory Read Datapath
2.6. MAX® 10 External Memory Write Datapath
2.7. MAX® 10 Address/Command Path
2.8. MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. MAX® 10 Low Power Feature
2.7. MAX® 10 Address/Command Path
Altera's soft memory controller IP and PHY IP operate at half rate and issue address/command instructions at half-rate.
- You must send the address/command instructions to the external DRAM center-aligned with respect to the external memory clock (CK/CK#).
- For LPDDR2 applications, the address/command path is double data rate (DDR). Dedicated DDIO output registers in the I/O periphery clocks out the address/command instructions to the external DRAM.
- For DDR2/3 applications, the address/command path is single data rate (SDR). Instead of dedicated DDIO output registers, simple output I/O registers in the I/O periphery clocks out the address/command instructions to the external DRAM device.